Lines Matching refs:i2c

3  * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
11 #include <linux/i2c.h>
272 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
274 	writel(readl(i2c->regs + HSI2C_INT_STATUS),
275 				i2c->regs + HSI2C_INT_STATUS);
288 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
300 	unsigned int clkin = clk_get_rate(i2c->clk);
301 	unsigned int op_clk = hs_timings ? i2c->op_clock :
302 		(i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ :
303 		i2c->op_clock;
320 	if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) {
321 		div = ((clkin / (16 * i2c->op_clock)) - 1);
324 			writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
326 			writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
371 	t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
372 	if (i2c->variant->hw == I2C_TYPE_EXYNOS8895)
374 	else if (i2c->variant->hw == I2C_TYPE_EXYNOS7)
380 	if (i2c->variant->hw == I2C_TYPE_EXYNOS8895)
386 		dev_err(i2c->dev, "%s clock set-up failed\n",
416 	dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
418 	dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
420 	dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
422 	dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
425 		writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
426 		writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
427 		writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
429 		writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
430 		writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
431 		writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
433 	writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
438 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
441 	int ret = exynos5_i2c_set_timing(i2c, false);
443 	if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ)
446 	return exynos5_i2c_set_timing(i2c, true);
453 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
455 	u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
456 	u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
460 	writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
463 					i2c->regs + HSI2C_CTL);
464 	writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
466 	if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) {
467 		writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
468 					i2c->regs + HSI2C_ADDR);
472 	writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
475 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
480 	i2c_ctl = readl(i2c->regs + HSI2C_CTL);
482 	writel(i2c_ctl, i2c->regs + HSI2C_CTL);
484 	i2c_ctl = readl(i2c->regs + HSI2C_CTL);
486 	writel(i2c_ctl, i2c->regs + HSI2C_CTL);
489 	exynos5_hsi2c_clock_setup(i2c);
491 	exynos5_i2c_init(i2c);
503 	struct exynos5_i2c *i2c = dev_id;
508 	i2c->state = -EINVAL;
510 	spin_lock(&i2c->lock);
512 	int_status = readl(i2c->regs + HSI2C_INT_STATUS);
513 	writel(int_status, i2c->regs + HSI2C_INT_STATUS);
516 	switch (i2c->variant->hw) {
523 			i2c->trans_done = 1;
524 			i2c->state = 0;
526 			dev_dbg(i2c->dev, "Deal with arbitration lose\n");
527 			i2c->state = -EAGAIN;
530 			dev_dbg(i2c->dev, "No ACK from device\n");
531 			i2c->state = -ENXIO;
534 			dev_dbg(i2c->dev, "No device\n");
535 			i2c->state = -ENXIO;
538 			dev_dbg(i2c->dev, "Accessing device timed out\n");
539 			i2c->state = -ETIMEDOUT;
548 		trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
550 			dev_dbg(i2c->dev, "No ACK from device\n");
551 			i2c->state = -ENXIO;
554 			dev_dbg(i2c->dev, "No device\n");
555 			i2c->state = -ENXIO;
558 			dev_dbg(i2c->dev, "Deal with arbitration lose\n");
559 			i2c->state = -EAGAIN;
562 			dev_dbg(i2c->dev, "Accessing device timed out\n");
563 			i2c->state = -ETIMEDOUT;
566 			i2c->trans_done = 1;
567 			i2c->state = 0;
573 	if ((i2c->msg->flags & I2C_M_RD) && (int_status &
575 		fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
577 		len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
581 				readl(i2c->regs + HSI2C_RX_DATA);
582 			i2c->msg->buf[i2c->msg_ptr++] = byte;
585 		i2c->state = 0;
587 		fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
590 		len = i2c->variant->fifo_depth - fifo_level;
591 		if (len > (i2c->msg->len - i2c->msg_ptr)) {
592 			u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
595 			writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
596 			len = i2c->msg->len - i2c->msg_ptr;
600 			byte = i2c->msg->buf[i2c->msg_ptr++];
601 			writel(byte, i2c->regs + HSI2C_TX_DATA);
604 		i2c->state = 0;
608 	if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
609 	    (i2c->state < 0)) {
610 		writel(0, i2c->regs + HSI2C_INT_ENABLE);
611 		exynos5_i2c_clr_pend_irq(i2c);
612 		complete(&i2c->msg_complete);
615 	spin_unlock(&i2c->lock);
628 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
636 		trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
646 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
650 	val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;
651 	writel(val, i2c->regs + HSI2C_CTL);
652 	val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;
653 	writel(val, i2c->regs + HSI2C_CONF);
660 	writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
661 	exynos5_i2c_wait_bus_idle(i2c);
662 	writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
663 	exynos5_i2c_wait_bus_idle(i2c);
665 	val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;
666 	writel(val, i2c->regs + HSI2C_CTL);
667 	val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;
668 	writel(val, i2c->regs + HSI2C_CONF);
671 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
675 	if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
685 		u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);
693 		exynos5_i2c_bus_recover(i2c);
699  * i2c: struct exynos5_i2c pointer for the current bus
707 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
717 	if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
722 	i2c_ctl = readl(i2c->regs + HSI2C_CTL);
726 	if (i2c->msg->flags & I2C_M_RD) {
731 		trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
732 			(i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
740 		trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
741 			(i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
747 	i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr);
749 	if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ)
750 		i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr));
752 	writel(i2c_addr, i2c->regs + HSI2C_ADDR);
754 	writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
755 	writel(i2c_ctl, i2c->regs + HSI2C_CTL);
757 	exynos5_i2c_bus_check(i2c);
763 	spin_lock_irqsave(&i2c->lock, flags);
764 	writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
768 	i2c_auto_conf |= i2c->msg->len;
770 	writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
771 	spin_unlock_irqrestore(&i2c->lock, flags);
774 static bool exynos5_i2c_poll_irqs_timeout(struct exynos5_i2c *i2c,
780 	       !((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
781 	         (i2c->state < 0))) {
782 		while (readl(i2c->regs + HSI2C_INT_ENABLE) &
783 		       readl(i2c->regs + HSI2C_INT_STATUS))
784 			exynos5_i2c_irq(i2c->irq, i2c);
790 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
796 	i2c->msg = msgs;
797 	i2c->msg_ptr = 0;
798 	i2c->trans_done = 0;
800 	reinit_completion(&i2c->msg_complete);
802 	exynos5_i2c_message_start(i2c, stop);
804 	if (!i2c->atomic)
805 		time_left = wait_for_completion_timeout(&i2c->msg_complete,
808 		time_left = exynos5_i2c_poll_irqs_timeout(i2c,
814 		ret = i2c->state;
821 		ret = exynos5_i2c_wait_bus_idle(i2c);
824 		exynos5_i2c_reset(i2c);
826 			dev_warn(i2c->dev, "%s timeout\n",
837 	struct exynos5_i2c *i2c = adap->algo_data;
840 	ret = clk_enable(i2c->pclk);
844 	ret = clk_enable(i2c->clk);
849 		ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);
854 	clk_disable(i2c->clk);
856 	clk_disable(i2c->pclk);
864 	struct exynos5_i2c *i2c = adap->algo_data;
867 	disable_irq(i2c->irq);
868 	i2c->atomic = true;
870 	i2c->atomic = false;
871 	enable_irq(i2c->irq);
890 	struct exynos5_i2c *i2c;
893 	i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
894 	if (!i2c)
897 	if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
898 		i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
900 	strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
901 	i2c->adap.owner   = THIS_MODULE;
902 	i2c->adap.algo    = &exynos5_i2c_algorithm;
903 	i2c->adap.retries = 3;
905 	i2c->dev = &pdev->dev;
906 	i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
907 	if (IS_ERR(i2c->clk)) {
912 	i2c->pclk = devm_clk_get_optional(&pdev->dev, "hsi2c_pclk");
913 	if (IS_ERR(i2c->pclk)) {
914 		return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),
918 	ret = clk_prepare_enable(i2c->pclk);
922 	ret = clk_prepare_enable(i2c->clk);
926 	i2c->regs = devm_platform_ioremap_resource(pdev, 0);
927 	if (IS_ERR(i2c->regs)) {
928 		ret = PTR_ERR(i2c->regs);
932 	i2c->adap.dev.of_node = np;
933 	i2c->adap.algo_data = i2c;
934 	i2c->adap.dev.parent = &pdev->dev;
937 	exynos5_i2c_clr_pend_irq(i2c);
939 	spin_lock_init(&i2c->lock);
940 	init_completion(&i2c->msg_complete);
942 	i2c->irq = ret = platform_get_irq(pdev, 0);
946 	ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
947 			       IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);
949 		dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
953 	i2c->variant = of_device_get_match_data(&pdev->dev);
955 	ret = exynos5_hsi2c_clock_setup(i2c);
959 	exynos5_i2c_reset(i2c);
961 	ret = i2c_add_adapter(&i2c->adap);
965 	platform_set_drvdata(pdev, i2c);
967 	clk_disable(i2c->clk);
968 	clk_disable(i2c->pclk);
973 	clk_disable_unprepare(i2c->clk);
976 	clk_disable_unprepare(i2c->pclk);
982 	struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
984 	i2c_del_adapter(&i2c->adap);
986 	clk_unprepare(i2c->clk);
987 	clk_unprepare(i2c->pclk);
992 	struct exynos5_i2c *i2c = dev_get_drvdata(dev);
994 	i2c_mark_adapter_suspended(&i2c->adap);
995 	clk_unprepare(i2c->clk);
996 	clk_unprepare(i2c->pclk);
1003 	struct exynos5_i2c *i2c = dev_get_drvdata(dev);
1006 	ret = clk_prepare_enable(i2c->pclk);
1010 	ret = clk_prepare_enable(i2c->clk);
1014 	ret = exynos5_hsi2c_clock_setup(i2c);
1018 	exynos5_i2c_init(i2c);
1019 	clk_disable(i2c->clk);
1020 	clk_disable(i2c->pclk);
1021 	i2c_mark_adapter_resumed(&i2c->adap);
1026 	clk_disable_unprepare(i2c->clk);
1028 	clk_disable_unprepare(i2c->pclk);