hwtracing/coresight/coresight-etm4x-sysfs.c

18 	struct etmv4_config *config = &drvdata->config;
20 	idx = config->addr_idx;
26 	if (FIELD_GET(TRCACATRn_TYPE_MASK, config->addr_acc[idx]) == TRCACATRn_TYPE_ADDR) {
35 		if (config->addr_type[idx] != ETM_ADDR_TYPE_RANGE ||
36 		    config->addr_type[idx + 1] != ETM_ADDR_TYPE_RANGE)
44 			config->viiectlr |= BIT(idx / 2 + 16);
45 			config->viiectlr &= ~BIT(idx / 2);
51 			config->viiectlr |= BIT(idx / 2);
52 			config->viiectlr &= ~BIT(idx / 2 + 16);
173 	struct etmv4_config *config = &drvdata->config;
180 		config->mode = 0x0;
183 	config->mode &= ~(ETM_MODE_LOAD | ETM_MODE_STORE);
184 	config->cfg &= ~(TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE);
187 	config->mode &= ~(ETM_MODE_DATA_TRACE_ADDR |
189 	config->cfg &= ~(TRCCONFIGR_DA | TRCCONFIGR_DV);
192 	config->eventctrl0 = 0x0;
193 	config->eventctrl1 = 0x0;
196 	config->ts_ctrl = 0x0;
199 	config->stall_ctrl = 0x0;
203 		config->syncfreq = 0x8;
210 	config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
212 		config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
214 		config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
218 	config->viiectlr = 0x0;
221 	config->vissctlr = 0x0;
222 	config->vipcssctlr = 0x0;
226 		config->seq_ctrl[i] = 0x0;
227 	config->seq_rst = 0x0;
228 	config->seq_state = 0x0;
231 	config->ext_inp = 0x0;
233 	config->cntr_idx = 0x0;
235 		config->cntrldvr[i] = 0x0;
236 		config->cntr_ctrl[i] = 0x0;
237 		config->cntr_val[i] = 0x0;
240 	config->res_idx = 0x0;
242 		config->res_ctrl[i] = 0x0;
244 	config->ss_idx = 0x0;
246 		config->ss_ctrl[i] = 0x0;
247 		config->ss_pe_cmp[i] = 0x0;
250 	config->addr_idx = 0x0;
252 		config->addr_val[i] = 0x0;
253 		config->addr_acc[i] = 0x0;
254 		config->addr_type[i] = ETM_ADDR_TYPE_NONE;
257 	config->ctxid_idx = 0x0;
259 		config->ctxid_pid[i] = 0x0;
261 	config->ctxid_mask0 = 0x0;
262 	config->ctxid_mask1 = 0x0;
264 	config->vmid_idx = 0x0;
266 		config->vmid_val[i] = 0x0;
267 	config->vmid_mask0 = 0x0;
268 	config->vmid_mask1 = 0x0;
287 	struct etmv4_config *config = &drvdata->config;
289 	val = config->mode;
299 	struct etmv4_config *config = &drvdata->config;
305 	config->mode = val & ETMv4_MODE_ALL;
309 		config->cfg  &= ~TRCCONFIGR_INSTP0_LOAD_STORE;
310 		if (config->mode & ETM_MODE_LOAD)
312 			config->cfg  |= TRCCONFIGR_INSTP0_LOAD;
313 		if (config->mode & ETM_MODE_STORE)
315 			config->cfg  |= TRCCONFIGR_INSTP0_STORE;
316 		if (config->mode & ETM_MODE_LOAD_STORE)
321 			config->cfg  |= TRCCONFIGR_INSTP0_LOAD_STORE;
325 	if ((config->mode & ETM_MODE_BB) && (drvdata->trcbb == true))
326 		config->cfg |= TRCCONFIGR_BB;
328 		config->cfg &= ~TRCCONFIGR_BB;
331 	if ((config->mode & ETMv4_MODE_CYCACC) &&
333 		config->cfg |= TRCCONFIGR_CCI;
335 		config->cfg &= ~TRCCONFIGR_CCI;
338 	if ((config->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size))
339 		config->cfg |= TRCCONFIGR_CID;
341 		config->cfg &= ~TRCCONFIGR_CID;
343 	if ((config->mode & ETM_MODE_VMID) && (drvdata->vmid_size))
344 		config->cfg |= TRCCONFIGR_VMID;
346 		config->cfg &= ~TRCCONFIGR_VMID;
349 	mode = ETM_MODE_COND(config->mode);
351 		config->cfg &= ~TRCCONFIGR_COND_MASK;
352 		config->cfg |= mode << __bf_shf(TRCCONFIGR_COND_MASK);
356 	if ((config->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size))
357 		config->cfg |= TRCCONFIGR_TS;
359 		config->cfg &= ~TRCCONFIGR_TS;
362 	if ((config->mode & ETM_MODE_RETURNSTACK) &&
364 		config->cfg |= TRCCONFIGR_RS;
366 		config->cfg &= ~TRCCONFIGR_RS;
369 	mode = ETM_MODE_QELEM(config->mode);
371 	config->cfg &= ~(TRCCONFIGR_QE_W_COUNTS | TRCCONFIGR_QE_WO_COUNTS);
378 		config->cfg |= TRCCONFIGR_QE_W_COUNTS;
384 		config->cfg |= TRCCONFIGR_QE_WO_COUNTS;
387 	if ((config->mode & ETM_MODE_ATB_TRIGGER) &&
389 		config->eventctrl1 |= TRCEVENTCTL1R_ATB;
391 		config->eventctrl1 &= ~TRCEVENTCTL1R_ATB;
394 	if ((config->mode & ETM_MODE_LPOVERRIDE) &&
396 		config->eventctrl1 |= TRCEVENTCTL1R_LPOVERRIDE;
398 		config->eventctrl1 &= ~TRCEVENTCTL1R_LPOVERRIDE;
401 	if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true))
402 		config->stall_ctrl |= TRCSTALLCTLR_ISTALL;
404 		config->stall_ctrl &= ~TRCSTALLCTLR_ISTALL;
407 	if (config->mode & ETM_MODE_INSTPRIO)
408 		config->stall_ctrl |= TRCSTALLCTLR_INSTPRIORITY;
410 		config->stall_ctrl &= ~TRCSTALLCTLR_INSTPRIORITY;
413 	if ((config->mode & ETM_MODE_NOOVERFLOW) &&
415 		config->stall_ctrl |= TRCSTALLCTLR_NOOVERFLOW;
417 		config->stall_ctrl &= ~TRCSTALLCTLR_NOOVERFLOW;
420 	if (config->mode & ETM_MODE_VIEWINST_STARTSTOP)
421 		config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
423 		config->vinst_ctrl &= ~TRCVICTLR_SSSTATUS;
426 	if (config->mode & ETM_MODE_TRACE_RESET)
427 		config->vinst_ctrl |= TRCVICTLR_TRCRESET;
429 		config->vinst_ctrl &= ~TRCVICTLR_TRCRESET;
432 	if ((config->mode & ETM_MODE_TRACE_ERR) &&
434 		config->vinst_ctrl |= TRCVICTLR_TRCERR;
436 		config->vinst_ctrl &= ~TRCVICTLR_TRCERR;
438 	if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
439 		etm4_config_trace_mode(config);
453 	struct etmv4_config *config = &drvdata->config;
455 	val = config->pe_sel;
465 	struct etmv4_config *config = &drvdata->config;
476 	config->pe_sel = val;
488 	struct etmv4_config *config = &drvdata->config;
490 	val = config->eventctrl0;
500 	struct etmv4_config *config = &drvdata->config;
509 		config->eventctrl0 = val & 0xFF;
513 		config->eventctrl0 = val & 0xFFFF;
517 		config->eventctrl0 = val & 0xFFFFFF;
521 		config->eventctrl0 = val;
537 	struct etmv4_config *config = &drvdata->config;
539 	val = FIELD_GET(TRCEVENTCTL1R_INSTEN_MASK, config->eventctrl1);
549 	struct etmv4_config *config = &drvdata->config;
556 	config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK;
560 		config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1;
564 		config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1);
568 		config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 |
574 		config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 |
593 	struct etmv4_config *config = &drvdata->config;
595 	val = config->ts_ctrl;
605 	struct etmv4_config *config = &drvdata->config;
612 	config->ts_ctrl = val & ETMv4_EVENT_MASK;
623 	struct etmv4_config *config = &drvdata->config;
625 	val = config->syncfreq;
635 	struct etmv4_config *config = &drvdata->config;
642 	config->syncfreq = val & ETMv4_SYNC_MASK;
653 	struct etmv4_config *config = &drvdata->config;
655 	val = config->ccctlr;
665 	struct etmv4_config *config = &drvdata->config;
675 	config->ccctlr = val;
686 	struct etmv4_config *config = &drvdata->config;
688 	val = config->bb_ctrl;
698 	struct etmv4_config *config = &drvdata->config;
715 	config->bb_ctrl = val & (TRCBBCTLR_MODE | TRCBBCTLR_RANGE_MASK);
726 	struct etmv4_config *config = &drvdata->config;
728 	val = FIELD_GET(TRCVICTLR_EVENT_MASK, config->vinst_ctrl);
738 	struct etmv4_config *config = &drvdata->config;
745 	config->vinst_ctrl &= ~TRCVICTLR_EVENT_MASK;
746 	config->vinst_ctrl |= FIELD_PREP(TRCVICTLR_EVENT_MASK, val);
758 	struct etmv4_config *config = &drvdata->config;
760 	val = FIELD_GET(TRCVICTLR_EXLEVEL_S_MASK, config->vinst_ctrl);
770 	struct etmv4_config *config = &drvdata->config;
777 	config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_S_MASK;
780 	config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_S_MASK);
792 	struct etmv4_config *config = &drvdata->config;
795 	val = FIELD_GET(TRCVICTLR_EXLEVEL_NS_MASK, config->vinst_ctrl);
805 	struct etmv4_config *config = &drvdata->config;
812 	config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_NS_MASK;
815 	config->vinst_ctrl |= val << __bf_shf(TRCVICTLR_EXLEVEL_NS_MASK);
827 	struct etmv4_config *config = &drvdata->config;
829 	val = config->addr_idx;
839 	struct etmv4_config *config = &drvdata->config;
851 	config->addr_idx = val;
864 	struct etmv4_config *config = &drvdata->config;
867 	idx = config->addr_idx;
868 	val = FIELD_GET(TRCACATRn_TYPE_MASK, config->addr_acc[idx]);
885 	struct etmv4_config *config = &drvdata->config;
893 	idx = config->addr_idx;
896 		config->addr_acc[idx] &= ~TRCACATRn_TYPE_MASK;
910 	struct etmv4_config *config = &drvdata->config;
912 	idx = config->addr_idx;
914 	if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
915 	      config->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
919 	val = (unsigned long)config->addr_val[idx];
931 	struct etmv4_config *config = &drvdata->config;
937 	idx = config->addr_idx;
938 	if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
939 	      config->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
944 	config->addr_val[idx] = (u64)val;
945 	config->addr_type[idx] = ETM_ADDR_TYPE_SINGLE;
958 	struct etmv4_config *config = &drvdata->config;
961 	idx = config->addr_idx;
966 	if (!((config->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
967 	       config->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
968 	      (config->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
969 	       config->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
974 	val1 = (unsigned long)config->addr_val[idx];
975 	val2 = (unsigned long)config->addr_val[idx + 1];
987 	struct etmv4_config *config = &drvdata->config;
1000 	idx = config->addr_idx;
1006 	if (!((config->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
1007 	       config->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
1008 	      (config->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
1009 	       config->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
1014 	config->addr_val[idx] = (u64)val1;
1015 	config->addr_type[idx] = ETM_ADDR_TYPE_RANGE;
1016 	config->addr_val[idx + 1] = (u64)val2;
1017 	config->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE;
1024 		exclude = config->mode & ETM_MODE_EXCLUDE;
1039 	struct etmv4_config *config = &drvdata->config;
1042 	idx = config->addr_idx;
1044 	if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1045 	      config->addr_type[idx] == ETM_ADDR_TYPE_START)) {
1050 	val = (unsigned long)config->addr_val[idx];
1062 	struct etmv4_config *config = &drvdata->config;
1068 	idx = config->addr_idx;
1073 	if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1074 	      config->addr_type[idx] == ETM_ADDR_TYPE_START)) {
1079 	config->addr_val[idx] = (u64)val;
1080 	config->addr_type[idx] = ETM_ADDR_TYPE_START;
1081 	config->vissctlr |= BIT(idx);
1094 	struct etmv4_config *config = &drvdata->config;
1097 	idx = config->addr_idx;
1099 	if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1100 	      config->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
1105 	val = (unsigned long)config->addr_val[idx];
1117 	struct etmv4_config *config = &drvdata->config;
1123 	idx = config->addr_idx;
1128 	if (!(config->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
1129 	       config->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
1134 	config->addr_val[idx] = (u64)val;
1135 	config->addr_type[idx] = ETM_ADDR_TYPE_STOP;
1136 	config->vissctlr |= BIT(idx + 16);
1149 	struct etmv4_config *config = &drvdata->config;
1152 	idx = config->addr_idx;
1154 	val = FIELD_GET(TRCACATRn_CONTEXTTYPE_MASK, config->addr_acc[idx]);
1169 	struct etmv4_config *config = &drvdata->config;
1177 	idx = config->addr_idx;
1180 		config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_MASK;
1184 			config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID;
1185 			config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_VMID;
1190 			config->addr_acc[idx] &= ~TRCACATRn_CONTEXTTYPE_CTXID;
1191 			config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID;
1199 			config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_CTXID;
1201 			config->addr_acc[idx] |= TRCACATRn_CONTEXTTYPE_VMID;
1215 	struct etmv4_config *config = &drvdata->config;
1218 	idx = config->addr_idx;
1220 	val = FIELD_GET(TRCACATRn_CONTEXT_MASK, config->addr_acc[idx]);
1232 	struct etmv4_config *config = &drvdata->config;
1243 	idx = config->addr_idx;
1245 	config->addr_acc[idx] &= ~TRCACATRn_CONTEXT_MASK;
1246 	config->addr_acc[idx] |= val << __bf_shf(TRCACATRn_CONTEXT_MASK);
1259 	struct etmv4_config *config = &drvdata->config;
1262 	idx = config->addr_idx;
1263 	val = FIELD_GET(TRCACATRn_EXLEVEL_MASK, config->addr_acc[idx]);
1275 	struct etmv4_config *config = &drvdata->config;
1284 	idx = config->addr_idx;
1286 	config->addr_acc[idx] &= ~TRCACATRn_EXLEVEL_MASK;
1287 	config->addr_acc[idx] |= val << __bf_shf(TRCACATRn_EXLEVEL_MASK);
1307 	struct etmv4_config *config = &drvdata->config;
1312 	idx = config->addr_idx;
1313 	addr_v = config->addr_val[idx];
1314 	addr_ctrl = config->addr_acc[idx];
1315 	addr_type = config->addr_type[idx];
1320 			addr_v = config->addr_val[idx];
1322 			addr_v2 = config->addr_val[idx + 1];
1324 		exclude = config->viiectlr & BIT(idx / 2 + 16);
1350 	struct etmv4_config *config = &drvdata->config;
1354 	val = config->vipcssctlr;
1363 	struct etmv4_config *config = &drvdata->config;
1371 	config->vipcssctlr = val;
1383 	struct etmv4_config *config = &drvdata->config;
1385 	val = config->seq_idx;
1395 	struct etmv4_config *config = &drvdata->config;
1407 	config->seq_idx = val;
1419 	struct etmv4_config *config = &drvdata->config;
1421 	val = config->seq_state;
1431 	struct etmv4_config *config = &drvdata->config;
1438 	config->seq_state = val;
1450 	struct etmv4_config *config = &drvdata->config;
1453 	idx = config->seq_idx;
1454 	val = config->seq_ctrl[idx];
1466 	struct etmv4_config *config = &drvdata->config;
1472 	idx = config->seq_idx;
1474 	config->seq_ctrl[idx] = val & 0xFFFF;
1486 	struct etmv4_config *config = &drvdata->config;
1488 	val = config->seq_rst;
1498 	struct etmv4_config *config = &drvdata->config;
1505 	config->seq_rst = val & ETMv4_EVENT_MASK;
1516 	struct etmv4_config *config = &drvdata->config;
1518 	val = config->cntr_idx;
1528 	struct etmv4_config *config = &drvdata->config;
1540 	config->cntr_idx = val;
1553 	struct etmv4_config *config = &drvdata->config;
1556 	idx = config->cntr_idx;
1557 	val = config->cntrldvr[idx];
1569 	struct etmv4_config *config = &drvdata->config;
1577 	idx = config->cntr_idx;
1578 	config->cntrldvr[idx] = val;
1591 	struct etmv4_config *config = &drvdata->config;
1594 	idx = config->cntr_idx;
1595 	val = config->cntr_val[idx];
1607 	struct etmv4_config *config = &drvdata->config;
1615 	idx = config->cntr_idx;
1616 	config->cntr_val[idx] = val;
1629 	struct etmv4_config *config = &drvdata->config;
1632 	idx = config->cntr_idx;
1633 	val = config->cntr_ctrl[idx];
1645 	struct etmv4_config *config = &drvdata->config;
1651 	idx = config->cntr_idx;
1652 	config->cntr_ctrl[idx] = val;
1664 	struct etmv4_config *config = &drvdata->config;
1666 	val = config->res_idx;
1676 	struct etmv4_config *config = &drvdata->config;
1692 	config->res_idx = val;
1705 	struct etmv4_config *config = &drvdata->config;
1708 	idx = config->res_idx;
1709 	val = config->res_ctrl[idx];
1721 	struct etmv4_config *config = &drvdata->config;
1727 	idx = config->res_idx;
1732 	config->res_ctrl[idx] = val & (TRCRSCTLRn_PAIRINV |
1746 	struct etmv4_config *config = &drvdata->config;
1748 	val = config->ss_idx;
1758 	struct etmv4_config *config = &drvdata->config;
1766 	config->ss_idx = val;
1778 	struct etmv4_config *config = &drvdata->config;
1781 	val = config->ss_ctrl[config->ss_idx];
1793 	struct etmv4_config *config = &drvdata->config;
1799 	idx = config->ss_idx;
1800 	config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
1802 	config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
1813 	struct etmv4_config *config = &drvdata->config;
1816 	val = config->ss_status[config->ss_idx];
1828 	struct etmv4_config *config = &drvdata->config;
1831 	val = config->ss_pe_cmp[config->ss_idx];
1843 	struct etmv4_config *config = &drvdata->config;
1849 	idx = config->ss_idx;
1850 	config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
1852 	config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
1864 	struct etmv4_config *config = &drvdata->config;
1866 	val = config->ctxid_idx;
1876 	struct etmv4_config *config = &drvdata->config;
1888 	config->ctxid_idx = val;
1901 	struct etmv4_config *config = &drvdata->config;
1911 	idx = config->ctxid_idx;
1912 	val = (unsigned long)config->ctxid_pid[idx];
1924 	struct etmv4_config *config = &drvdata->config;
1949 	idx = config->ctxid_idx;
1950 	config->ctxid_pid[idx] = (u64)pid;
1962 	struct etmv4_config *config = &drvdata->config;
1972 	val1 = config->ctxid_mask0;
1973 	val2 = config->ctxid_mask1;
1985 	struct etmv4_config *config = &drvdata->config;
2015 		config->ctxid_mask0 = val1 & 0xFF;
2019 		config->ctxid_mask0 = val1 & 0xFFFF;
2023 		config->ctxid_mask0 = val1 & 0xFFFFFF;
2027 		config->ctxid_mask0 = val1;
2031 		config->ctxid_mask0 = val1;
2032 		config->ctxid_mask1 = val2 & 0xFF;
2036 		config->ctxid_mask0 = val1;
2037 		config->ctxid_mask1 = val2 & 0xFFFF;
2041 		config->ctxid_mask0 = val1;
2042 		config->ctxid_mask1 = val2 & 0xFFFFFF;
2046 		config->ctxid_mask0 = val1;
2047 		config->ctxid_mask1 = val2;
2058 	mask = config->ctxid_mask0;
2068 				config->ctxid_pid[i] &= ~(0xFFUL << (j * 8));
2074 			mask = config->ctxid_mask1;
2090 	struct etmv4_config *config = &drvdata->config;
2092 	val = config->vmid_idx;
2102 	struct etmv4_config *config = &drvdata->config;
2114 	config->vmid_idx = val;
2126 	struct etmv4_config *config = &drvdata->config;
2136 	val = (unsigned long)config->vmid_val[config->vmid_idx];
2147 	struct etmv4_config *config = &drvdata->config;
2166 	config->vmid_val[config->vmid_idx] = (u64)val;
2177 	struct etmv4_config *config = &drvdata->config;
2187 	val1 = config->vmid_mask0;
2188 	val2 = config->vmid_mask1;
2200 	struct etmv4_config *config = &drvdata->config;
2230 		config->vmid_mask0 = val1 & 0xFF;
2234 		config->vmid_mask0 = val1 & 0xFFFF;
2238 		config->vmid_mask0 = val1 & 0xFFFFFF;
2242 		config->vmid_mask0 = val1;
2246 		config->vmid_mask0 = val1;
2247 		config->vmid_mask1 = val2 & 0xFF;
2251 		config->vmid_mask0 = val1;
2252 		config->vmid_mask1 = val2 & 0xFFFF;
2256 		config->vmid_mask0 = val1;
2257 		config->vmid_mask1 = val2 & 0xFFFFFF;
2261 		config->vmid_mask0 = val1;
2262 		config->vmid_mask1 = val2;
2274 	mask = config->vmid_mask0;
2284 				config->vmid_val[i] &= ~(0xFFUL << (j * 8));
2290 			mask = config->vmid_mask1;