Lines Matching refs:div_h
156 u64 div_h, div_l, duty_cycle_period, dividend;
162 div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val);
172 << div_h;
177 << div_h;
192 u64 div_h, div_l, divisor, expect_period;
200 * Pick the smallest value for div_h so that div_l can be the biggest
205 div_h = order_base_2(DIV64_U64_ROUND_UP(priv->clk_rate * expect_period, divisor));
206 if (div_h > 0xf)
207 div_h = 0xf;
209 divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
220 dev_dbg(pwmchip_parent(chip), "clk source: %ld div_h %lld, div_l : %lld\n",
221 priv->clk_rate, div_h, div_l);
224 (u64)NSEC_PER_SEC * (div_l + 1) << div_h);
257 val |= FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |