drm/xe/xe_hw_error.c

24 #define PVC_ERROR_MASK_SET(hw_err, err_bit)	((hw_err == HARDWARE_ERROR_CORRECTABLE) ? \
56 #define PVC_GT_VECTOR_LEN(hw_err)	((hw_err == HARDWARE_ERROR_CORRECTABLE) ? \
59 static enum drm_xe_ras_error_severity hw_err_to_severity(const enum hardware_error hw_err)
61 	if (hw_err == HARDWARE_ERROR_CORRECTABLE)
159 #define PVC_MASTER_LOCAL_REG_INFO(hw_err)	((hw_err == HARDWARE_ERROR_FATAL) ? \
179 static void csc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
181 	const enum drm_xe_ras_error_severity severity = hw_err_to_severity(hw_err);
261 static void gt_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err,
264 	const enum drm_xe_ras_error_severity severity = hw_err_to_severity(hw_err);
275 	if (hw_err == HARDWARE_ERROR_NONFATAL) {
281 	for (i = 0; i < PVC_GT_VECTOR_LEN(hw_err); i++) {
284 		vector = xe_mmio_read32(mmio, ERR_STAT_GT_VECTOR_REG(hw_err, i));
304 			err_stat = xe_mmio_read32(mmio, ERR_STAT_GT_REG(hw_err));
306 				if (PVC_ERROR_MASK_SET(hw_err, errbit))
310 				xe_mmio_write32(mmio, ERR_STAT_GT_REG(hw_err), err_stat);
333 		xe_mmio_write32(mmio, ERR_STAT_GT_VECTOR_REG(hw_err, i), vector);
337 static void soc_slave_ieh_handler(struct xe_tile *tile, const enum hardware_error hw_err, u32 error_id)
339 	const enum drm_xe_ras_error_severity severity = hw_err_to_severity(hw_err);
345 	slave_global_errstat = xe_mmio_read32(mmio, SOC_GLOBAL_ERR_STAT_REG(slave, hw_err));
348 		slave_local_errstat = xe_mmio_read32(mmio, SOC_LOCAL_ERR_STAT_REG(slave, hw_err));
350 		if (hw_err == HARDWARE_ERROR_FATAL) {
356 		xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(slave, hw_err),
363 	xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(slave, hw_err), slave_global_errstat);
366 static void soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err,
369 	const enum drm_xe_ras_error_severity severity = hw_err_to_severity(hw_err);
384 		xe_mmio_write32(mmio, SOC_GSYSEVTCTL_REG(master, slave, i), ~REG_BIT(hw_err));
386 	if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
387 		xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(master, hw_err), REG_GENMASK(31, 0));
388 		xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(master, hw_err), REG_GENMASK(31, 0));
389 		xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(slave, hw_err), REG_GENMASK(31, 0));
390 		xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(slave, hw_err), REG_GENMASK(31, 0));
399 	master_global_errstat = xe_mmio_read32(mmio, SOC_GLOBAL_ERR_STAT_REG(master, hw_err));
401 		soc_slave_ieh_handler(tile, hw_err, error_id);
404 		master_local_errstat = xe_mmio_read32(mmio, SOC_LOCAL_ERR_STAT_REG(master, hw_err));
407 			log_soc_error(tile, PVC_MASTER_LOCAL_REG_INFO(hw_err), severity, regbit, error_id);
409 		xe_mmio_write32(mmio, SOC_LOCAL_ERR_STAT_REG(master, hw_err), master_local_errstat);
415 	xe_mmio_write32(mmio, SOC_GLOBAL_ERR_STAT_REG(master, hw_err), master_global_errstat);
423 static void hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
425 	const enum drm_xe_ras_error_severity severity = hw_err_to_severity(hw_err);
437 	err_src = xe_mmio_read32(&tile->mmio, DEV_ERR_STAT_REG(hw_err));
451 		csc_hw_error_handler(tile, hw_err);
487 			gt_hw_error_handler(tile, hw_err, error_id);
489 			soc_hw_error_handler(tile, hw_err, error_id);
493 	xe_mmio_write32(&tile->mmio, DEV_ERR_STAT_REG(hw_err), err_src);
510 	enum hardware_error hw_err;
515 	for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++) {
516 		if (master_ctl & ERROR_IRQ(hw_err))
517 			hw_error_source_handler(tile, hw_err);