drm/vc4/vc4_render_cl.c

56 static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val)
58 	*(u8 *)(setup->rcl->vaddr + setup->next_offset) = val;
59 	setup->next_offset += 1;
62 static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val)
64 	*(u16 *)(setup->rcl->vaddr + setup->next_offset) = val;
65 	setup->next_offset += 2;
68 static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val)
70 	*(u32 *)(setup->rcl->vaddr + setup->next_offset) = val;
71 	setup->next_offset += 4;
80 static void vc4_store_before_load(struct vc4_rcl_setup *setup)
82 	rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
83 	rcl_u16(setup,
89 	rcl_u32(setup, 0); /* no address, since we're in None mode */
115 static void vc4_tile_coordinates(struct vc4_rcl_setup *setup,
118 	rcl_u8(setup, VC4_PACKET_TILE_COORDINATES);
119 	rcl_u8(setup, x);
120 	rcl_u8(setup, y);
124 		      struct vc4_rcl_setup *setup,
134 	if (setup->color_read) {
137 			rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
138 			rcl_u32(setup,
139 				vc4_full_res_offset(exec, setup->color_read,
143 			rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
144 			rcl_u16(setup, args->color_read.bits);
145 			rcl_u32(setup, setup->color_read->dma_addr +
150 	if (setup->zs_read) {
151 		if (setup->color_read) {
153 			vc4_tile_coordinates(setup, x, y);
154 			vc4_store_before_load(setup);
159 			rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
160 			rcl_u32(setup,
161 				vc4_full_res_offset(exec, setup->zs_read,
165 			rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
166 			rcl_u16(setup, args->zs_read.bits);
167 			rcl_u32(setup, setup->zs_read->dma_addr +
175 	vc4_tile_coordinates(setup, x, y);
181 		rcl_u8(setup, VC4_PACKET_WAIT_ON_SEMAPHORE);
184 		rcl_u8(setup, VC4_PACKET_BRANCH_TO_SUB_LIST);
185 		rcl_u32(setup, (exec->tile_alloc_offset +
189 	if (setup->msaa_color_write) {
190 		bool last_tile_write = (!setup->msaa_zs_write &&
191 					!setup->zs_write &&
192 					!setup->color_write);
199 		rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
200 		rcl_u32(setup,
201 			vc4_full_res_offset(exec, setup->msaa_color_write,
206 	if (setup->msaa_zs_write) {
207 		bool last_tile_write = (!setup->zs_write &&
208 					!setup->color_write);
211 		if (setup->msaa_color_write)
212 			vc4_tile_coordinates(setup, x, y);
217 		rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
218 		rcl_u32(setup,
219 			vc4_full_res_offset(exec, setup->msaa_zs_write,
224 	if (setup->zs_write) {
225 		bool last_tile_write = !setup->color_write;
227 		if (setup->msaa_color_write || setup->msaa_zs_write)
228 			vc4_tile_coordinates(setup, x, y);
230 		rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
231 		rcl_u16(setup, args->zs_write.bits |
234 		rcl_u32(setup,
235 			(setup->zs_write->dma_addr + args->zs_write.offset) |
240 	if (setup->color_write) {
241 		if (setup->msaa_color_write || setup->msaa_zs_write ||
242 		    setup->zs_write) {
243 			vc4_tile_coordinates(setup, x, y);
247 			rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
249 			rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER);
254 			     struct vc4_rcl_setup *setup)
285 	if (setup->color_read) {
293 	if (setup->zs_read) {
294 		if (setup->color_read) {
312 	if (setup->msaa_color_write)
314 	if (setup->msaa_zs_write)
317 	if (setup->zs_write)
319 	if (setup->color_write)
324 		((setup->msaa_color_write != NULL) +
325 		 (setup->msaa_zs_write != NULL) +
326 		 (setup->color_write != NULL) +
327 		 (setup->zs_write != NULL) - 1);
331 	setup->rcl = &vc4_bo_create(dev, size, true, VC4_BO_TYPE_RCL)->base;
332 	if (IS_ERR(setup->rcl))
333 		return PTR_ERR(setup->rcl);
334 	list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head,
343 		rcl_u8(setup, VC4_PACKET_CLEAR_COLORS);
344 		rcl_u32(setup, args->clear_color[0]);
345 		rcl_u32(setup, args->clear_color[1]);
346 		rcl_u32(setup, args->clear_z);
347 		rcl_u8(setup, args->clear_s);
349 		vc4_tile_coordinates(setup, 0, 0);
351 		rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
352 		rcl_u16(setup, VC4_LOADSTORE_TILE_BUFFER_NONE);
353 		rcl_u32(setup, 0); /* no address, since we're in None mode */
356 	rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
357 	rcl_u32(setup,
358 		(setup->color_write ? (setup->color_write->dma_addr +
361 	rcl_u16(setup, args->width);
362 	rcl_u16(setup, args->height);
363 	rcl_u16(setup, args->color_write.bits);
372 			emit_tile(exec, setup, x, y, first, last);
376 	BUG_ON(setup->next_offset != size);
377 	exec->ct1ca = setup->rcl->dma_addr;
378 	exec->ct1ea = setup->rcl->dma_addr + setup->next_offset;
535 				    struct vc4_rcl_setup *setup,
597 	struct vc4_rcl_setup setup = {0};
623 	ret = vc4_rcl_render_config_surface_setup(exec, &setup,
624 						  &setup.color_write,
629 	ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read,
634 	ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read,
639 	ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write,
644 	ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write,
649 	ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write,
657 	if (!setup.color_write && !setup.zs_write &&
658 	    !setup.msaa_color_write && !setup.msaa_zs_write) {
663 	return vc4_create_rcl_bo(dev, exec, &setup);