Lines Matching defs:dispc
514 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val)
516 iowrite32(val, dispc->base_common + reg);
519 static u32 dispc_read(struct dispc_device *dispc, u16 reg)
521 return ioread32(dispc->base_common + reg);
525 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)
527 void __iomem *base = dispc->base_vid[hw_plane];
532 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg)
534 void __iomem *base = dispc->base_vid[hw_plane];
539 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport,
542 void __iomem *base = dispc->base_ovr[hw_videoport];
547 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
549 void __iomem *base = dispc->base_ovr[hw_videoport];
554 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport,
557 void __iomem *base = dispc->base_vp[hw_videoport];
562 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
564 void __iomem *base = dispc->base_vp[hw_videoport];
575 dispc_vp_write(tidss->dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
577 while (!(oldi_reset_bit & dispc_read(tidss->dispc, DSS_SYSSTATUS)) &&
581 if (!(oldi_reset_bit & dispc_read(tidss->dispc, DSS_SYSSTATUS)))
589 dispc_vp_write(tidss->dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
617 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end)
619 return FLD_GET(dispc_read(dispc, idx), start, end);
622 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val,
625 dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val,
629 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx,
632 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end);
635 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx,
638 dispc_vid_write(dispc, hw_plane, idx,
639 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx),
643 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx,
646 return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end);
649 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val,
652 dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx),
657 static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx,
660 return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end);
663 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx,
666 dispc_ovr_write(dispc, ovr, idx,
667 FLD_MOD(dispc_ovr_read(dispc, ovr, idx),
723 static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc,
726 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS);
731 static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc,
736 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat);
739 static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc,
742 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS);
747 static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc,
752 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat);
755 static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc,
758 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE);
763 static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc,
768 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat);
771 static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc,
774 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE);
779 static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc,
784 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat);
787 static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc,
790 dispc_k2g_vp_write_irqstatus(dispc, 0, mask);
791 dispc_k2g_vid_write_irqstatus(dispc, 0, mask);
795 dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc)
800 dispc_write(dispc, DISPC_IRQSTATUS,
801 dispc_read(dispc, DISPC_IRQSTATUS));
803 stat |= dispc_k2g_vp_read_irqstatus(dispc, 0);
804 stat |= dispc_k2g_vid_read_irqstatus(dispc, 0);
806 dispc_k2g_clear_irqstatus(dispc, stat);
811 static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc)
815 stat |= dispc_k2g_vp_read_irqenable(dispc, 0);
816 stat |= dispc_k2g_vid_read_irqenable(dispc, 0);
822 void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
824 dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc);
827 dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask);
829 dispc_k2g_vp_set_irqenable(dispc, 0, mask);
830 dispc_k2g_vid_set_irqenable(dispc, 0, mask);
832 dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7));
835 dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & old_mask);
838 dispc_k2g_read_irqenable(dispc);
841 static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc,
844 u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport));
849 static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc,
854 dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat);
857 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,
860 u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
861 u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_id));
866 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc,
869 u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
872 dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_id), stat);
875 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc,
878 u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport));
883 static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc,
888 dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat);
891 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,
894 u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
895 u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_id));
900 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc,
903 u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
906 dispc_write(dispc, DISPC_VID_IRQENABLE(hw_id), stat);
910 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)
914 for (i = 0; i < dispc->feat->num_vps; ++i) {
916 dispc_k3_vp_write_irqstatus(dispc, i, clearmask);
919 for (i = 0; i < dispc->feat->num_vids; ++i) {
921 dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
925 dispc_write(dispc, DISPC_IRQSTATUS, dispc_read(dispc, DISPC_IRQSTATUS));
928 dispc_read(dispc, DISPC_IRQSTATUS);
932 dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc)
937 for (i = 0; i < dispc->feat->num_vps; ++i)
938 status |= dispc_k3_vp_read_irqstatus(dispc, i);
940 for (i = 0; i < dispc->feat->num_vids; ++i)
941 status |= dispc_k3_vid_read_irqstatus(dispc, i);
943 dispc_k3_clear_irqstatus(dispc, status);
948 static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc)
953 for (i = 0; i < dispc->feat->num_vps; ++i)
954 enable |= dispc_k3_vp_read_irqenable(dispc, i);
956 for (i = 0; i < dispc->feat->num_vids; ++i)
957 enable |= dispc_k3_vid_read_irqenable(dispc, i);
962 static void dispc_k3_set_irqenable(struct dispc_device *dispc,
969 old_mask = dispc_k3_read_irqenable(dispc);
972 dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask);
974 for (i = 0; i < dispc->feat->num_vps; ++i) {
975 dispc_k3_vp_set_irqenable(dispc, i, mask);
982 for (i = 0; i < dispc->feat->num_vids; ++i) {
983 u32 hw_id = dispc->feat->vid_info[i].hw_id;
985 dispc_k3_vid_set_irqenable(dispc, i, mask);
994 dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable);
997 dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable);
1000 dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & old_mask);
1003 dispc_read(dispc, DISPC_IRQENABLE_SET);
1006 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)
1008 switch (dispc->feat->subrev) {
1010 return dispc_k2g_read_and_clear_irqstatus(dispc);
1016 return dispc_k3_read_and_clear_irqstatus(dispc);
1023 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
1025 switch (dispc->feat->subrev) {
1027 dispc_k2g_set_irqenable(dispc, mask);
1034 dispc_k3_set_irqenable(dispc, mask);
1062 struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc,
1076 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
1082 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1085 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n",
1090 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI_AM65X &&
1092 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n",
1093 __func__, dispc->feat->vp_name[hw_videoport]);
1100 static void dispc_am65x_oldi_tx_power(struct dispc_device *dispc, bool power)
1104 if (WARN_ON(!dispc->am65x_oldi_io_ctrl))
1107 regmap_update_bits(dispc->am65x_oldi_io_ctrl, AM65X_OLDI_DAT0_IO_CTRL,
1109 regmap_update_bits(dispc->am65x_oldi_io_ctrl, AM65X_OLDI_DAT1_IO_CTRL,
1111 regmap_update_bits(dispc->am65x_oldi_io_ctrl, AM65X_OLDI_DAT2_IO_CTRL,
1113 regmap_update_bits(dispc->am65x_oldi_io_ctrl, AM65X_OLDI_DAT3_IO_CTRL,
1115 regmap_update_bits(dispc->am65x_oldi_io_ctrl, AM65X_OLDI_CLK_IO_CTRL,
1119 static void dispc_set_num_datalines(struct dispc_device *dispc,
1142 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8);
1145 static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_videoport,
1160 dev_warn(dispc->dev, "%s: %d port width not supported\n",
1171 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
1173 while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&
1177 if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)))
1178 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n",
1182 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
1188 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1194 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI_AM65X) {
1195 dispc_am65x_oldi_tx_power(dispc, true);
1197 dispc_enable_am65x_oldi(dispc, hw_videoport, fmt);
1201 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
1210 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1216 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);
1226 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
1231 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
1253 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI_AM65X)
1256 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ,
1265 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
1269 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);
1272 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport)
1274 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0);
1277 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport)
1279 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI_AM65X) {
1280 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
1282 dispc_am65x_oldi_tx_power(dispc, false);
1286 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport)
1288 return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5);
1291 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport)
1293 WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5));
1294 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5);
1337 static void dispc_vp_set_default_color(struct dispc_device *dispc,
1344 dispc_ovr_write(dispc, hw_videoport,
1346 dispc_ovr_write(dispc, hw_videoport,
1350 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
1358 bus_type = dispc->feat->vp_bus_type[hw_videoport];
1360 max_pclk = dispc->feat->max_pclk_khz[bus_type];
1365 if (mode->clock < dispc->feat->min_pclk_khz)
1409 if (dispc->memory_bandwidth_limit) {
1417 if (dispc->memory_bandwidth_limit < bandwidth)
1424 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport)
1426 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]);
1429 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__,
1435 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
1437 clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
1451 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
1457 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate);
1459 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n",
1464 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]);
1467 dev_warn(dispc->dev,
1471 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n",
1472 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate);
1478 static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc,
1483 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION,
1487 static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc,
1491 u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
1493 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1495 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1497 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1501 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
1505 u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
1507 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1509 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1511 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1515 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
1518 switch (dispc->feat->subrev) {
1520 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport,
1527 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,
1531 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport,
1540 void dispc_ovr_enable_layer(struct dispc_device *dispc,
1543 if (dispc->feat->subrev == DISPC_K2G)
1546 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1629 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1644 dev_warn(dispc->dev, "%s: No post offset support for %s\n",
1648 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1652 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1667 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1749 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane,
1756 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n",
1761 if (dispc->feat->subrev == DISPC_K2G)
1762 dispc_k2g_vid_write_csc(dispc, hw_plane, coef);
1764 dispc_k3_vid_write_csc(dispc, hw_plane, coef);
1767 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane,
1770 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9);
1787 static void dispc_vid_write_fir_coefs(struct dispc_device *dispc,
1811 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__);
1819 dispc_vid_write(dispc, hw_plane, reg, c0);
1831 dispc_vid_write(dispc, hw_plane, reg, c12);
1856 static int dispc_vid_calc_scaling(struct dispc_device *dispc,
1861 const struct dispc_features_scaling *f = &dispc->feat->scaling;
1910 dev_dbg(dispc->dev,
1923 dev_dbg(dispc->dev,
1940 dev_dbg(dispc->dev,
1961 dev_dbg(dispc->dev,
1979 dev_dbg(dispc->dev,
1995 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev,
2003 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev,
2010 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc,
2014 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc,
2020 static void dispc_vid_set_scaling(struct dispc_device *dispc,
2026 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
2030 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
2038 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
2043 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,
2045 dispc_vid_write_fir_coefs(dispc, hw_plane,
2050 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2,
2052 dispc_vid_write_fir_coefs(dispc, hw_plane,
2059 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc);
2060 dispc_vid_write_fir_coefs(dispc, hw_plane,
2066 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc);
2067 dispc_vid_write_fir_coefs(dispc, hw_plane,
2120 static void dispc_plane_set_pixel_format(struct dispc_device *dispc,
2127 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
2137 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len)
2139 WARN_ON(!dispc->fourccs);
2141 *len = dispc->num_fourccs;
2143 return dispc->fourccs;
2159 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
2163 bool lite = dispc->feat->vid_info[hw_plane].is_lite;
2173 dev_dbg(dispc->dev,
2183 dev_dbg(dispc->dev,
2190 ret = dispc_vid_calc_scaling(dispc, state, &scaling, false);
2230 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
2234 bool lite = dispc->feat->vid_info[hw_plane].is_lite;
2241 dispc_vid_calc_scaling(dispc, state, &scale, lite);
2243 dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);
2245 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);
2246 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);
2247 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);
2248 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);
2250 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
2255 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2258 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2261 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,
2271 dispc_vid_write(dispc, hw_plane,
2273 dispc_vid_write(dispc, hw_plane,
2275 dispc_vid_write(dispc, hw_plane,
2277 dispc_vid_write(dispc, hw_plane,
2280 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV,
2287 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE,
2291 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc);
2296 dispc_vid_csc_setup(dispc, hw_plane, state);
2297 dispc_vid_csc_enable(dispc, hw_plane, true);
2299 dispc_vid_csc_enable(dispc, hw_plane, false);
2302 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,
2306 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2309 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2313 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable)
2315 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0);
2318 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane)
2320 return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0);
2323 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc,
2326 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD,
2330 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc,
2333 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD,
2337 static void dispc_k2g_plane_init(struct dispc_device *dispc)
2341 dev_dbg(dispc->dev, "%s()\n", __func__);
2344 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2346 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2348 for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) {
2349 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2362 dev_dbg(dispc->dev,
2364 dispc->feat->vid_info[hw_plane].name,
2370 dispc_vid_set_buf_threshold(dispc, hw_plane,
2372 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2375 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2382 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2387 static void dispc_k3_plane_init(struct dispc_device *dispc)
2393 dev_dbg(dispc->dev, "%s()\n", __func__);
2395 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0);
2396 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3);
2399 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2401 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2403 for (hw_plane = 0; hw_plane < dispc->feat->num_vids; hw_plane++) {
2404 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2417 dev_dbg(dispc->dev,
2419 dispc->feat->vid_info[hw_plane].name,
2425 dispc_vid_set_buf_threshold(dispc, hw_plane,
2427 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2430 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2433 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2438 static void dispc_plane_init(struct dispc_device *dispc)
2440 switch (dispc->feat->subrev) {
2442 dispc_k2g_plane_init(dispc);
2449 dispc_k3_plane_init(dispc);
2456 static void dispc_vp_init(struct dispc_device *dispc)
2460 dev_dbg(dispc->dev, "%s()\n", __func__);
2463 for (i = 0; i < dispc->feat->num_vps; i++)
2464 VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2);
2467 static void dispc_initial_config(struct dispc_device *dispc)
2469 dispc_plane_init(dispc);
2470 dispc_vp_init(dispc);
2473 if (dispc->feat->subrev == DISPC_J721E) {
2474 dispc_write(dispc, DISPC_CONNECTIONS,
2481 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc,
2484 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2485 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2488 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2490 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2498 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE,
2503 static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc,
2506 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2507 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2510 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2512 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2520 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2524 static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc,
2527 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2528 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2531 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2533 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT))
2542 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2546 static void dispc_vp_write_gamma_table(struct dispc_device *dispc,
2549 switch (dispc->feat->subrev) {
2551 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport);
2557 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport);
2560 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport);
2573 static void dispc_vp_set_gamma(struct dispc_device *dispc,
2578 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2579 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2583 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n",
2586 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT)
2620 dispc_vp_write_gamma_table(dispc, hw_videoport);
2667 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2680 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i],
2684 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2693 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr);
2697 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2732 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2746 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i],
2750 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2759 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc);
2763 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2767 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc,
2784 dispc_vp_set_gamma(dispc, hw_videoport, lut, length);
2789 if (dispc->feat->subrev == DISPC_K2G)
2790 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm);
2792 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm);
2795 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
2798 dispc_vp_set_default_color(dispc, hw_videoport, 0);
2799 dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset);
2802 int dispc_runtime_suspend(struct dispc_device *dispc)
2804 dev_dbg(dispc->dev, "suspend\n");
2806 dispc->is_enabled = false;
2808 clk_disable_unprepare(dispc->fclk);
2813 int dispc_runtime_resume(struct dispc_device *dispc)
2815 dev_dbg(dispc->dev, "resume\n");
2817 clk_prepare_enable(dispc->fclk);
2819 if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0)
2820 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n");
2822 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n",
2823 dispc_read(dispc, DSS_REVISION));
2825 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n",
2826 REG_GET(dispc, DSS_SYSSTATUS, 1, 1),
2827 REG_GET(dispc, DSS_SYSSTATUS, 2, 2),
2828 REG_GET(dispc, DSS_SYSSTATUS, 3, 3));
2830 if (dispc->feat->subrev == DISPC_AM625 ||
2831 dispc->feat->subrev == DISPC_AM65X)
2832 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n",
2833 REG_GET(dispc, DSS_SYSSTATUS, 5, 5),
2834 REG_GET(dispc, DSS_SYSSTATUS, 6, 6),
2835 REG_GET(dispc, DSS_SYSSTATUS, 7, 7));
2837 dev_dbg(dispc->dev, "DISPC IDLE %d\n",
2838 REG_GET(dispc, DSS_SYSSTATUS, 9, 9));
2840 dispc_initial_config(dispc);
2842 dispc->is_enabled = true;
2844 tidss_irq_resume(dispc->tidss);
2853 tidss->dispc = NULL;
2873 struct dispc_device *dispc)
2875 dispc->am65x_oldi_io_ctrl =
2878 if (PTR_ERR(dispc->am65x_oldi_io_ctrl) == -ENODEV) {
2879 dispc->am65x_oldi_io_ctrl = NULL;
2880 } else if (IS_ERR(dispc->am65x_oldi_io_ctrl)) {
2882 __func__, PTR_ERR(dispc->am65x_oldi_io_ctrl));
2883 return PTR_ERR(dispc->am65x_oldi_io_ctrl);
2888 static void dispc_init_errata(struct dispc_device *dispc)
2896 dispc->errata.i2000 = true;
2897 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n");
2905 static void dispc_softreset_k2g(struct dispc_device *dispc)
2909 spin_lock_irqsave(&dispc->tidss->irq_lock, flags);
2910 dispc_set_irqenable(dispc, 0);
2911 dispc_read_and_clear_irqstatus(dispc);
2912 spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags);
2914 for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx)
2915 VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0);
2918 static int dispc_softreset(struct dispc_device *dispc)
2923 if (dispc->feat->subrev == DISPC_K2G) {
2924 dispc_softreset_k2g(dispc);
2929 REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
2931 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS,
2934 dev_err(dispc->dev, "failed to reset dispc\n");
2941 static int dispc_init_hw(struct dispc_device *dispc)
2943 struct device *dev = dispc->dev;
2952 ret = clk_prepare_enable(dispc->fclk);
2958 ret = dispc_softreset(dispc);
2962 clk_disable_unprepare(dispc->fclk);
2972 clk_disable_unprepare(dispc->fclk);
2988 struct dispc_device *dispc;
3005 dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL);
3006 if (!dispc)
3009 dispc->tidss = tidss;
3010 dispc->dev = dev;
3011 dispc->feat = feat;
3013 dispc_init_errata(dispc);
3015 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats),
3016 sizeof(*dispc->fourccs), GFP_KERNEL);
3017 if (!dispc->fourccs)
3022 if (dispc->errata.i2000 &&
3026 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc;
3029 dispc->num_fourccs = num_fourccs;
3031 dispc_common_regmap = dispc->feat->common_regs;
3033 r = dispc_iomap_resource(pdev, dispc->feat->common,
3034 &dispc->base_common);
3038 for (i = 0; i < dispc->feat->num_vids; i++) {
3039 r = dispc_iomap_resource(pdev, dispc->feat->vid_info[i].name,
3040 &dispc->base_vid[i]);
3045 for (i = 0; i < dispc->feat->num_vps; i++) {
3046 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size;
3050 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i],
3051 &dispc->base_ovr[i]);
3055 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i],
3056 &dispc->base_vp[i]);
3060 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]);
3063 dispc->feat->vpclk_name[i], PTR_ERR(clk));
3066 dispc->vp_clk[i] = clk;
3073 dispc->vp_data[i].gamma_table = gamma_table;
3077 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc);
3082 dispc->fclk = devm_clk_get(dev, "fck");
3083 if (IS_ERR(dispc->fclk)) {
3085 __func__, PTR_ERR(dispc->fclk));
3086 return PTR_ERR(dispc->fclk);
3088 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk));
3090 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth",
3091 &dispc->memory_bandwidth_limit);
3093 r = dispc_init_hw(dispc);
3097 tidss->dispc = dispc;