drm/tegra/dp.c

34 static void drm_dp_link_reset(struct drm_dp_link *link)
38 	if (!link)
41 	link->revision = 0;
42 	link->max_rate = 0;
43 	link->max_lanes = 0;
45 	drm_dp_link_caps_reset(&link->caps);
46 	link->aux_rd_interval.cr = 0;
47 	link->aux_rd_interval.ce = 0;
48 	link->edp = 0;
50 	link->rate = 0;
51 	link->lanes = 0;
54 		link->rates[i] = 0;
56 	link->num_rates = 0;
61  * @link: the link to add the rate to
64  * Add a link rate to the list of supported link rates.
69  * - EEXISTS if the link already supports this rate
74 int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate)
78 	if (link->num_rates == DP_MAX_SUPPORTED_RATES)
81 	for (pivot = 0; pivot < link->num_rates; pivot++)
82 		if (rate <= link->rates[pivot])
85 	if (pivot != link->num_rates && rate == link->rates[pivot])
88 	for (i = link->num_rates; i > pivot; i--)
89 		link->rates[i] = link->rates[i - 1];
91 	link->rates[pivot] = rate;
92 	link->num_rates++;
99  * @link: the link from which to remove the rate
102  * Removes a link rate from the list of supported link rates.
111 int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate)
115 	for (i = 0; i < link->num_rates; i++)
116 		if (rate == link->rates[i])
119 	if (i == link->num_rates)
122 	link->num_rates--;
124 	while (i < link->num_rates) {
125 		link->rates[i] = link->rates[i + 1];
133  * drm_dp_link_update_rates() - normalize the supported link rates array
134  * @link: the link for which to normalize the supported link rates
137  * of supported link rates. This function removes any stale entries, compacts
138  * the array and updates the supported link rate count. Note that calling the
144 void drm_dp_link_update_rates(struct drm_dp_link *link)
148 	for (i = 0; i < link->num_rates; i++) {
149 		if (link->rates[i] != 0)
150 			link->rates[count++] = link->rates[i];
153 	for (i = count; i < link->num_rates; i++)
154 		link->rates[i] = 0;
156 	link->num_rates = count;
160  * drm_dp_link_probe() - probe a DisplayPort link for capabilities
162  * @link: pointer to structure in which to return link capabilities
166  * configure the link based on the link's capabilities.
170 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
176 	drm_dp_link_reset(link);
182 	link->revision = dpcd[DP_DPCD_REV];
183 	link->max_rate = drm_dp_max_link_rate(dpcd);
184 	link->max_lanes = drm_dp_max_lane_count(dpcd);
186 	link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd);
187 	link->caps.tps3_supported = drm_dp_tps3_supported(dpcd);
188 	link->caps.fast_training = drm_dp_fast_training_cap(dpcd);
189 	link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd);
192 		link->caps.alternate_scrambler_reset = true;
201 			link->edp = drm_dp_edp_revisions[value];
226 	if (rd_interval == 0 || link->revision >= DP_DPCD_REV_14)
227 		link->aux_rd_interval.cr = 100;
230 		link->aux_rd_interval.ce = 400;
232 	link->rate = link->max_rate;
233 	link->lanes = link->max_lanes;
236 	if (link->edp >= 0x14) {
251 			drm_dp_link_add_rate(link, rate * 200);
259  * drm_dp_link_configure() - configure a DisplayPort link
261  * @link: pointer to a structure containing the link configuration
265 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
270 	if (link->ops && link->ops->configure) {
271 		err = link->ops->configure(link);
273 			DRM_ERROR("failed to configure DP link: %d\n", err);
278 	values[0] = drm_dp_link_rate_to_bw_code(link->rate);
279 	values[1] = link->lanes;
281 	if (link->caps.enhanced_framing)
288 	if (link->caps.channel_coding)
297 	if (link->caps.alternate_scrambler_reset) {
309  * @link: DRM DP link object
314  * with the lowest number of lanes and the lowest possible link rate that can
320 int drm_dp_link_choose(struct drm_dp_link *link,
324 	/* available link symbol clock rates */
329 	unsigned int rate = link->max_rate;
335 	for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) {
341 			 * Link rates in the DRM DP helpers are really link
343 			 * of the link.
351 				link->lanes = lanes[i];
352 				link->rate = rates[j];
365  * link training.
369  * drm_dp_link_train_init() - initialize DisplayPort link training state
370  * @train: DisplayPort link training state
399 static int drm_dp_link_apply_training(struct drm_dp_link *link)
401 	struct drm_dp_link_train_set *request = &link->train.request;
402 	unsigned int lanes = link->lanes, *vs, *pe, *pc, i;
403 	struct drm_dp_aux *aux = link->aux;
407 	err = link->ops->apply_training(link);
409 		DRM_ERROR("failed to apply link training: %d\n", err);
429 	if (link->revision >= 0x12 && link->rate == 540000) {
443 	/* write link pattern */
444 	if (link->train.pattern != DP_TRAINING_PATTERN_DISABLE)
447 	pattern |= link->train.pattern;
458 static void drm_dp_link_train_wait(struct drm_dp_link *link)
462 	switch (link->train.pattern) {
464 		min = link->aux_rd_interval.cr;
469 		min = link->aux_rd_interval.ce;
480 static void drm_dp_link_get_adjustments(struct drm_dp_link *link,
483 	struct drm_dp_link_train_set *adjust = &link->train.adjust;
488 	err = drm_dp_dpcd_read(link->aux, DP_ADJUST_REQUEST_POST_CURSOR2,
495 	for (i = 0; i < link->lanes; i++) {
528 static int drm_dp_link_recover_clock(struct drm_dp_link *link)
533 	err = drm_dp_link_apply_training(link);
537 	drm_dp_link_train_wait(link);
539 	err = drm_dp_dpcd_read_link_status(link->aux, status);
541 		DRM_ERROR("failed to read link status: %d\n", err);
545 	if (!drm_dp_clock_recovery_ok(status, link->lanes))
546 		drm_dp_link_get_adjustments(link, status);
548 		link->train.clock_recovered = true;
553 static int drm_dp_link_clock_recovery(struct drm_dp_link *link)
559 	link->train.pattern = DP_TRAINING_PATTERN_1;
562 		err = drm_dp_link_recover_clock(link);
568 		if (link->train.clock_recovered)
571 		drm_dp_link_train_adjust(&link->train);
577 static int drm_dp_link_equalize_channel(struct drm_dp_link *link)
579 	struct drm_dp_aux *aux = link->aux;
583 	err = drm_dp_link_apply_training(link);
587 	drm_dp_link_train_wait(link);
591 		DRM_ERROR("failed to read link status: %d\n", err);
595 	if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
597 		link->train.clock_recovered = false;
601 	if (!drm_dp_channel_eq_ok(status, link->lanes))
602 		drm_dp_link_get_adjustments(link, status);
604 		link->train.channel_equalized = true;
609 static int drm_dp_link_channel_equalization(struct drm_dp_link *link)
615 	if (link->caps.tps3_supported)
616 		link->train.pattern = DP_TRAINING_PATTERN_3;
618 		link->train.pattern = DP_TRAINING_PATTERN_2;
621 		err = drm_dp_link_equalize_channel(link);
627 		if (link->train.channel_equalized)
630 		drm_dp_link_train_adjust(&link->train);
636 static int drm_dp_link_downgrade(struct drm_dp_link *link)
638 	switch (link->rate) {
643 		link->rate = 162000;
647 		link->rate = 270000;
654 static void drm_dp_link_train_disable(struct drm_dp_link *link)
658 	link->train.pattern = DP_TRAINING_PATTERN_DISABLE;
660 	err = drm_dp_link_apply_training(link);
662 		DRM_ERROR("failed to disable link training: %d\n", err);
665 static int drm_dp_link_train_full(struct drm_dp_link *link)
670 	DRM_DEBUG_KMS("full-training link: %u lane%s at %u MHz\n",
671 		      link->lanes, (link->lanes > 1) ? "s" : "",
672 		      link->rate / 100);
674 	err = drm_dp_link_configure(link->aux, link);
676 		DRM_ERROR("failed to configure DP link: %d\n", err);
680 	err = drm_dp_link_clock_recovery(link);
686 	if (!link->train.clock_recovered) {
687 		DRM_ERROR("clock recovery failed, downgrading link\n");
689 		err = drm_dp_link_downgrade(link);
698 	err = drm_dp_link_channel_equalization(link);
704 	if (!link->train.channel_equalized) {
705 		DRM_ERROR("channel equalization failed, downgrading link\n");
707 		err = drm_dp_link_downgrade(link);
717 	drm_dp_link_train_disable(link);
721 static int drm_dp_link_train_fast(struct drm_dp_link *link)
726 	DRM_DEBUG_KMS("fast-training link: %u lane%s at %u MHz\n",
727 		      link->lanes, (link->lanes > 1) ? "s" : "",
728 		      link->rate / 100);
730 	err = drm_dp_link_configure(link->aux, link);
732 		DRM_ERROR("failed to configure DP link: %d\n", err);
737 	link->train.pattern = DP_TRAINING_PATTERN_1;
739 	err = drm_dp_link_apply_training(link);
746 	if (link->caps.tps3_supported)
747 		link->train.pattern = DP_TRAINING_PATTERN_3;
749 		link->train.pattern = DP_TRAINING_PATTERN_2;
751 	err = drm_dp_link_apply_training(link);
757 	err = drm_dp_dpcd_read_link_status(link->aux, status);
759 		DRM_ERROR("failed to read link status: %d\n", err);
763 	if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
768 	if (!drm_dp_channel_eq_ok(status, link->lanes)) {
774 	drm_dp_link_train_disable(link);
779  * drm_dp_link_train() - perform DisplayPort link training
780  * @link: a DP link object
782  * Uses the context stored in the DP link object to perform link training. It
783  * is expected that drivers will call drm_dp_link_probe() to obtain the link
784  * capabilities before performing link training.
786  * If the sink supports fast link training (no AUX CH handshake) and valid
788  * link training and fall back to full link training on failure.
792 int drm_dp_link_train(struct drm_dp_link *link)
796 	drm_dp_link_train_init(&link->train);
798 	if (link->caps.fast_training) {
799 		if (drm_dp_link_train_valid(&link->train)) {
800 			err = drm_dp_link_train_fast(link);
802 				DRM_ERROR("fast link training failed: %d\n",
810 		DRM_DEBUG_KMS("fast link training not supported\n");
813 	err = drm_dp_link_train_full(link);
815 		DRM_ERROR("full link training failed: %d\n", err);