drm/rockchip/dw-mipi-dsi-rockchip.c

294 	const struct rockchip_dw_dsi_chip_data *cdata;
739 	if (dsi->cdata->lanecfg1_grf_reg)
740 		regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
741 					      dsi->cdata->lanecfg1);
743 	if (dsi->cdata->lanecfg2_grf_reg)
744 		regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
745 					      dsi->cdata->lanecfg2);
747 	if (dsi->cdata->enable_grf_reg)
748 		regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
749 					      dsi->cdata->enable);
755 	if (dsi->cdata->lcdsel_grf_reg)
756 		regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
757 			mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
1150 	if (dsi->cdata->dphy_rx_init) {
1161 		ret = dsi->cdata->dphy_rx_init(phy);
1249 	if (dsi->cdata->dphy_rx_power_on) {
1250 		ret = dsi->cdata->dphy_rx_power_on(phy);
1298 	if (dsi->cdata->dphy_rx_power_off) {
1299 		ret = dsi->cdata->dphy_rx_power_off(phy);
1357 	const struct rockchip_dw_dsi_chip_data *cdata =
1372 	while (cdata[i].reg) {
1373 		if (cdata[i].reg == res->start) {
1374 			dsi->cdata = &cdata[i];
1381 	if (!dsi->cdata) {
1418 	if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1428 	if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1445 	dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;