Lines Matching refs:WREG32
46 WREG32(VCE_CLOCK_GATING_B, tmp);
50 WREG32(VCE_UENC_CLOCK_GATING, tmp);
54 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
56 WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
61 WREG32(VCE_CLOCK_GATING_B, tmp);
66 WREG32(VCE_UENC_CLOCK_GATING, tmp);
70 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
86 WREG32(VCE_CLOCK_GATING_B, tmp);
92 WREG32(VCE_UENC_CLOCK_GATING, tmp);
97 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
100 WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
105 WREG32(VCE_CGTT_CLK_OVERRIDE, 7);
139 WREG32(VCE_CLOCK_GATING_A, tmp);
144 WREG32(VCE_UENC_CLOCK_GATING, tmp);
149 WREG32(VCE_CLOCK_GATING_B, tmp);
166 WREG32(VCE_CLOCK_GATING_B, 0xf7);
168 WREG32(VCE_LMI_CTRL, 0x00398000);
170 WREG32(VCE_LMI_SWAP_CNTL, 0);
171 WREG32(VCE_LMI_SWAP_CNTL1, 0);
172 WREG32(VCE_LMI_VM_CTRL, 0);
174 WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
178 WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
179 WREG32(VCE_VCPU_CACHE_SIZE0, size);
183 WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
184 WREG32(VCE_VCPU_CACHE_SIZE1, size);
188 WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
189 WREG32(VCE_VCPU_CACHE_SIZE2, size);