drm/radeon/uvd_v1_0.c

70 	WREG32(UVD_RBC_RB_WPTR, ring->wptr);
123 	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
124 	WREG32(UVD_VCPU_CACHE_SIZE0, size);
128 	WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
129 	WREG32(UVD_VCPU_CACHE_SIZE1, size);
134 	WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
135 	WREG32(UVD_VCPU_CACHE_SIZE2, size);
139 	WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
143 	WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
145 	WREG32(UVD_FW_START, *((uint32_t *)rdev->uvd.cpu_addr));
217 			WREG32(MC_CONFIG, 0);
218 			WREG32(MC_CONFIG, 1 << 4);
219 			WREG32(RS_DQ_RD_RET_CONF, 0x3f);
220 			WREG32(MC_CONFIG, 0x1f);
274 	WREG32(UVD_CGC_GATE, 0);
285 	WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
295 	WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
303 	WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);
304 	WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);
306 	WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
307 	WREG32(UVD_MPC_SET_MUXA1, 0x0);
308 	WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);
309 	WREG32(UVD_MPC_SET_MUXB1, 0x0);
310 	WREG32(UVD_MPC_SET_ALU, 0);
311 	WREG32(UVD_MPC_SET_MUX, 0x88);
314 	WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
318 	WREG32(UVD_VCPU_CNTL,  1 << 9);
326 	WREG32(UVD_SOFT_RESET, 0);
358 	WREG32(UVD_RBC_RB_CNTL, 0x11010101);
361 	WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
364 	WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
368 	WREG32(UVD_RBC_RB_RPTR, 0x0);
371 	WREG32(UVD_RBC_RB_WPTR, ring->wptr);
374 	WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
394 	WREG32(UVD_RBC_RB_CNTL, 0x11010101);
402 	WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
406 	WREG32(UVD_VCPU_CNTL, 0x0);
427 	WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);