drm/radeon/rv770_dpm.c

58 	struct rv7xx_power_info *pi = rdev->pm.dpm.priv;
60 	return pi;
65 	struct evergreen_power_info *pi = rdev->pm.dpm.priv;
67 	return pi;
73 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
82 		if (!pi->boot_in_gen2) {
147 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
160 		if (pi->mgcgtssm)
239 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
242 					 pi->soft_regs_start + reg_offset,
243 					 value, pi->sram_end);
250 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
253 					  pi->soft_regs_start + reg_offset,
254 					  value, pi->sram_end);
262 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
273 	a_n = (int)state->medium.sclk * pi->lmp +
274 		(int)state->low.sclk * (R600_AH_DFLT - pi->rlp);
275 	a_d = (int)state->low.sclk * (100 - (int)pi->rlp) +
276 		(int)state->medium.sclk * pi->lmp;
278 	l[1] = (u8)(pi->lmp - (int)pi->lmp * a_n / a_d);
279 	r[0] = (u8)(pi->rlp + (100 - (int)pi->rlp) * a_n / a_d);
281 	a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk *
282 		(R600_AH_DFLT - pi->rmp);
283 	a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) +
284 		(int)state->high.sclk * pi->lhp;
286 	l[2] = (u8)(pi->lhp - (int)pi->lhp * a_n / a_d);
287 	r[1] = (u8)(pi->rmp + (100 - (int)pi->rmp) * a_n / a_d);
290 		a_t = CG_R(r[i] * pi->bsp / 200) | CG_L(l[i] * pi->bsp / 200);
294 	a_t = CG_R(r[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200) |
295 		CG_L(l[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200);
307 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
311 		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
314 		cpu_to_be32(pi->psp);
391 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
394 		pi->clk_regs.rv770.mpll_ad_func_cntl;
396 		pi->clk_regs.rv770.mpll_ad_func_cntl_2;
398 		pi->clk_regs.rv770.mpll_dq_func_cntl;
400 		pi->clk_regs.rv770.mpll_dq_func_cntl_2;
402 		pi->clk_regs.rv770.mclk_pwrmgt_cntl;
403 	u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;
420 							 pi->mem_gddr5,
445 	if (pi->mem_gddr5) {
448 								 pi->mem_gddr5,
489 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
492 		pi->clk_regs.rv770.cg_spll_func_cntl;
494 		pi->clk_regs.rv770.cg_spll_func_cntl_2;
496 		pi->clk_regs.rv770.cg_spll_func_cntl_3;
498 		pi->clk_regs.rv770.cg_spll_spread_spectrum;
500 		pi->clk_regs.rv770.cg_spll_spread_spectrum_2;
539 	if (pi->sclk_ss) {
570 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
573 	if (!pi->voltage_control) {
579 	for (i = 0; i < pi->valid_vddc_entries; i++) {
580 		if (vddc <= pi->vddc_table[i].vddc) {
581 			voltage->index = pi->vddc_table[i].vddc_index;
587 	if (i == pi->valid_vddc_entries)
596 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
598 	if (!pi->mvdd_control) {
604 	if (mclk <= pi->mvdd_split_frequency) {
620 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
623 	level->gen2PCIE = pi->pcie_gen2 ?
642 		if (pi->mem_gddr5) {
643 			if (pl->mclk <= pi->mclk_strobe_mode_threshold)
649 			if (pl->mclk > pi->mclk_edc_enable_threshold)
744 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
758 		STATE0(64 * high_clock / pi->boot_sclk) |
765 		POWERMODE0(rv770_calculate_memory_refresh_rate(rdev, pi->boot_sclk)) |
784 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
787 		if (pi->sclk_ss)
790 		if (pi->mclk_ss) {
808 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
810 	if ((rdev->family == CHIP_RV770) && !pi->mem_gddr5) {
812 		       (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) |
819 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
822 	r600_calculate_u_and_p(pi->asi,
825 			       &pi->bsp,
826 			       &pi->bsu);
828 	r600_calculate_u_and_p(pi->pasi,
831 			       &pi->pbsp,
832 			       &pi->pbsu);
834 	pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
835 	pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
837 	WREG32(CG_BSP, pi->dsp);
891 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
893 	WREG32(CG_FTV, pi->vrc);
903 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
909 	ret = rv770_load_smc_ucode(rdev, pi->sram_end);
919 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
922 		pi->clk_regs.rv770.mpll_ad_func_cntl;
924 		pi->clk_regs.rv770.mpll_ad_func_cntl_2;
926 		pi->clk_regs.rv770.mpll_dq_func_cntl;
928 		pi->clk_regs.rv770.mpll_dq_func_cntl_2;
930 		pi->clk_regs.rv770.cg_spll_func_cntl;
932 		pi->clk_regs.rv770.cg_spll_func_cntl_2;
934 		pi->clk_regs.rv770.cg_spll_func_cntl_3;
942 	if (pi->acpi_vddc) {
943 		rv770_populate_vddc_value(rdev, pi->acpi_vddc,
945 		if (pi->pcie_gen2) {
946 			if (pi->acpi_pcie_gen2)
952 		if (pi->acpi_pcie_gen2)
957 		rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
1010 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1012 	if ((pi->s0_vid_lower_smio_cntl & pi->mvdd_mask_low) ==
1013 	     (pi->mvdd_low_smio[MVDD_LOW_INDEX] & pi->mvdd_mask_low)) {
1029 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1033 		cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);
1035 		cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);
1037 		cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);
1039 		cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);
1041 		cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);
1043 		cpu_to_be32(pi->clk_regs.rv770.dll_cntl);
1046 		cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
1048 		cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);
1054 		cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
1056 		cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
1058 		cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
1060 		cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);
1062 		cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);
1081 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1083 	if (pi->boot_in_gen2)
1093 		if (pi->mem_gddr5) {
1094 			if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold)
1100 			if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold)
1118 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1121 	for (i = 0; i < pi->valid_vddc_entries; i++) {
1122 		table->highSMIO[pi->vddc_table[i].vddc_index] =
1123 			pi->vddc_table[i].high_smio;
1124 		table->lowSMIO[pi->vddc_table[i].vddc_index] =
1125 			cpu_to_be32(pi->vddc_table[i].low_smio);
1130 		cpu_to_be32(pi->vddc_mask_low);
1133 	     ((i < pi->valid_vddc_entries) &&
1134 	      (pi->max_vddc_in_table >
1135 	       pi->vddc_table[i].vddc));
1139 		pi->vddc_table[i].vddc_index;
1147 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1149 	if (pi->mvdd_control) {
1151 			cpu_to_be32(pi->mvdd_low_smio[MVDD_HIGH_INDEX]);
1153 			cpu_to_be32(pi->mvdd_low_smio[MVDD_LOW_INDEX]);
1157 			cpu_to_be32(pi->mvdd_mask_low);
1166 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1168 	RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1173 	pi->boot_sclk = boot_state->low.sclk;
1205 	if (pi->mem_gddr5)
1227 				       pi->state_table_start,
1230 				       pi->sram_end);
1235 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1253 		pi->vddc_table[i].vddc = (u16)(min + i * step);
1255 						      pi->vddc_table[i].vddc,
1258 		pi->vddc_table[i].low_smio = gpio_pins & gpio_mask;
1259 		pi->vddc_table[i].high_smio = 0;
1260 		pi->vddc_mask_low = gpio_mask;
1262 			if ((pi->vddc_table[i].low_smio !=
1263 			     pi->vddc_table[i - 1].low_smio) ||
1264 			     (pi->vddc_table[i].high_smio !=
1265 			      pi->vddc_table[i - 1].high_smio))
1268 		pi->vddc_table[i].vddc_index = vddc_index;
1271 	pi->valid_vddc_entries = (u8)steps;
1286 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1292 	pi->mvdd_mask_low = gpio_mask;
1293 	pi->mvdd_low_smio[MVDD_HIGH_INDEX] =
1299 	pi->mvdd_low_smio[MVDD_LOW_INDEX] =
1312 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1319 		pi->mvdd_control = false;
1323 	pi->mvdd_split_frequency =
1326 	if (pi->mvdd_split_frequency == 0) {
1327 		pi->mvdd_control = false;
1386 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1387 	u16 address = pi->state_table_start +
1398 				       pi->sram_end);
1520 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1522 	pi->clk_regs.rv770.cg_spll_func_cntl =
1524 	pi->clk_regs.rv770.cg_spll_func_cntl_2 =
1526 	pi->clk_regs.rv770.cg_spll_func_cntl_3 =
1528 	pi->clk_regs.rv770.cg_spll_spread_spectrum =
1530 	pi->clk_regs.rv770.cg_spll_spread_spectrum_2 =
1532 	pi->clk_regs.rv770.mpll_ad_func_cntl =
1534 	pi->clk_regs.rv770.mpll_ad_func_cntl_2 =
1536 	pi->clk_regs.rv770.mpll_dq_func_cntl =
1538 	pi->clk_regs.rv770.mpll_dq_func_cntl_2 =
1540 	pi->clk_regs.rv770.mclk_pwrmgt_cntl =
1542 	pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);
1557 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1559 	pi->s0_vid_lower_smio_cntl =
1565 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1583 		vid_smio_cntl = pi->s0_vid_lower_smio_cntl;
1593 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1600 		pi->mem_gddr5 = true;
1602 		pi->mem_gddr5 = false;
1608 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1615 		pi->pcie_gen2 = true;
1617 		pi->pcie_gen2 = false;
1619 	if (pi->pcie_gen2) {
1621 			pi->boot_in_gen2 = true;
1623 			pi->boot_in_gen2 = false;
1625 		pi->boot_in_gen2 = false;
1631 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1633 	if (pi->gfx_clock_gating) {
1650 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1664 	if (pi->gfx_clock_gating)
1673 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1677 	pi->mclk_odt_threshold = 0;
1687 			pi->mclk_odt_threshold = 30000;
1693 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1697 		pi->max_vddc = 0;
1699 		pi->max_vddc = vddc;
1749 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1755 	if (pi->mclk_odt_threshold == 0)
1758 	if (current_state->high.mclk <= pi->mclk_odt_threshold)
1761 	if (new_state->high.mclk <= pi->mclk_odt_threshold)
1778 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1784 	if (pi->mclk_odt_threshold == 0)
1787 	if (current_state->high.mclk <= pi->mclk_odt_threshold)
1790 	if (new_state->high.mclk <= pi->mclk_odt_threshold)
1805 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1807 	if (pi->mclk_odt_threshold == 0)
1816 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1844 		if (pi->thermal_protection)
1855 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1858 		if (!(pi->active_auto_throttle_sources & (1 << source))) {
1859 			pi->active_auto_throttle_sources |= 1 << source;
1860 			rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1863 		if (pi->active_auto_throttle_sources & (1 << source)) {
1864 			pi->active_auto_throttle_sources &= ~(1 << source);
1865 			rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1897 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1901 	if (pi->gfx_clock_gating)
1907 	if (pi->voltage_control) {
1916 	if (pi->dcodt)
1919 	if (pi->mvdd_control) {
1932 	if (pi->thermal_protection)
1945 	if (pi->dynamic_pcie_gen2)
1967 	if (pi->gfx_clock_gating)
1970 	if (pi->mg_clock_gating)
2002 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2009 	if (pi->thermal_protection)
2014 	if (pi->dynamic_pcie_gen2)
2023 	if (pi->gfx_clock_gating)
2026 	if (pi->mg_clock_gating)
2040 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2062 	if (pi->dcodt)
2074 	if (pi->dcodt)
2084 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2088 	if (pi->dcodt)
2091 	if (pi->dcodt)
2098 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2103 	if (pi->dcodt)
2179 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2222 		if (pi->max_vddc)
2223 			pl->vddc = pi->max_vddc;
2227 		pi->acpi_vddc = pl->vddc;
2231 			pi->acpi_pcie_gen2 = true;
2233 			pi->acpi_pcie_gen2 = false;
2243 	if (pi->min_vddc_in_table > pl->vddc)
2244 		pi->min_vddc_in_table = pl->vddc;
2246 	if (pi->max_vddc_in_table < pl->vddc)
2247 		pi->max_vddc_in_table = pl->vddc;
2331 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2334 	pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2336 	pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2339 	if (pi->sclk_ss || pi->mclk_ss)
2340 		pi->dynamic_ss = true;
2342 		pi->dynamic_ss = false;
2347 	struct rv7xx_power_info *pi;
2351 	pi = kzalloc(sizeof(struct rv7xx_power_info), GFP_KERNEL);
2352 	if (pi == NULL)
2354 	rdev->pm.dpm.priv = pi;
2358 	pi->acpi_vddc = 0;
2359 	pi->min_vddc_in_table = 0;
2360 	pi->max_vddc_in_table = 0;
2378 		pi->ref_div = dividers.ref_div + 1;
2380 		pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
2382 	pi->mclk_strobe_mode_threshold = 30000;
2383 	pi->mclk_edc_enable_threshold = 30000;
2385 	pi->rlp = RV770_RLP_DFLT;
2386 	pi->rmp = RV770_RMP_DFLT;
2387 	pi->lhp = RV770_LHP_DFLT;
2388 	pi->lmp = RV770_LMP_DFLT;
2390 	pi->voltage_control =
2393 	pi->mvdd_control =
2398 	pi->asi = RV770_ASI_DFLT;
2399 	pi->pasi = RV770_HASI_DFLT;
2400 	pi->vrc = RV770_VRC_DFLT;
2402 	pi->power_gating = false;
2404 	pi->gfx_clock_gating = true;
2406 	pi->mg_clock_gating = true;
2407 	pi->mgcgtssm = true;
2409 	pi->dynamic_pcie_gen2 = true;
2412 		pi->thermal_protection = true;
2414 		pi->thermal_protection = false;
2416 	pi->display_gap = true;
2419 		pi->dcodt = true;
2421 		pi->dcodt = false;
2423 	pi->ulps = true;
2425 	pi->mclk_stutter_mode_threshold = 0;
2427 	pi->sram_end = SMC_RAM_END;
2428 	pi->state_table_start = RV770_SMC_TABLE_ADDRESS;
2429 	pi->soft_regs_start = RV770_SMC_SOFT_REGISTERS_START;