Lines Matching full:pi

41 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
43 	u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
44 	u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
45 	u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
46 	u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum;
47 	u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2;
88 	if (pi->sclk_ss) {
120 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
121 	u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl;
122 	u32 dll_cntl = pi->clk_regs.rv730.dll_cntl;
123 	u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
124 	u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
125 	u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
126 	u32 mpll_ss = pi->clk_regs.rv730.mpll_ss;
127 	u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2;
163 	if (pi->mclk_ss) {
197 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
199 	pi->clk_regs.rv730.cg_spll_func_cntl =
201 	pi->clk_regs.rv730.cg_spll_func_cntl_2 =
203 	pi->clk_regs.rv730.cg_spll_func_cntl_3 =
205 	pi->clk_regs.rv730.cg_spll_spread_spectrum =
207 	pi->clk_regs.rv730.cg_spll_spread_spectrum_2 =
210 	pi->clk_regs.rv730.mclk_pwrmgt_cntl =
212 	pi->clk_regs.rv730.dll_cntl =
214 	pi->clk_regs.rv730.mpll_func_cntl =
216 	pi->clk_regs.rv730.mpll_func_cntl2 =
218 	pi->clk_regs.rv730.mpll_func_cntl3 =
220 	pi->clk_regs.rv730.mpll_ss =
222 	pi->clk_regs.rv730.mpll_ss2 =
229 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
242 	if (pi->acpi_vddc) {
243 		rv770_populate_vddc_value(rdev, pi->acpi_vddc,
245 		table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
246 			pi->acpi_pcie_gen2 : 0;
248 			pi->acpi_pcie_gen2;
250 		rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
255 	mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
256 	mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
257 	mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
284 	spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
285 	spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
286 	spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
321 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
325 		cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl);
327 		cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2);
329 		cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3);
331 		cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl);
333 		cpu_to_be32(pi->clk_regs.rv730.dll_cntl);
335 		cpu_to_be32(pi->clk_regs.rv730.mpll_ss);
337 		cpu_to_be32(pi->clk_regs.rv730.mpll_ss2);
343 		cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl);
345 		cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2);
347 		cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3);
349 		cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum);
351 		cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2);
371 	table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
373 	if (pi->boot_in_gen2)
475 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
481 	mc4_io_pad_cntl |= pi->odt_value_0[i];
487 	mc4_io_pad_cntl |= pi->odt_value_1[i];
494 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
497 	pi->odt_value_0[0] = (u8)0;
498 	pi->odt_value_1[0] = (u8)0x80;
501 	pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff);
504 	pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff);