Lines Matching refs:const_ptr

243 	const struct radeon_tv_mode_constants *const_ptr;
259 			const_ptr = &available_tv_modes[0];
261 			const_ptr = &available_tv_modes[2];
264 			const_ptr = &available_tv_modes[1];
266 			const_ptr = &available_tv_modes[3];
268 	return const_ptr;
432 	const struct radeon_tv_mode_constants *const_ptr;
434 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
435 	if (!const_ptr)
438 	h_total = const_ptr->hor_total;
439 	v_total = const_ptr->ver_total;
473 	h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000;
476 	restart = const_ptr->def_restart;
492 		  const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
509 		h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) /
512 		h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) /
531 	const struct radeon_tv_mode_constants *const_ptr;
545 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq);
546 	if (!const_ptr)
608 		vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME;
610 		vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME;
620 	if (const_ptr->hor_resolution == 1024)
626 	tmp = const_ptr->ver_total * 2 * 1000;
777 	WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);
778 	WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);
779 	WREG32(RADEON_TV_HSTART, const_ptr->hor_start);
781 	WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);
782 	WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);
830 	const struct radeon_tv_mode_constants *const_ptr;
833 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
834 	if (!const_ptr)
837 	*h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
838 		(((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
842 	tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
843 		(const_ptr->hor_syncstart & 7);
846 	*v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) |
847 		((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
851 	tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
877 	const struct radeon_tv_mode_constants *const_ptr;
879 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
880 	if (!const_ptr)
883 	*htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN;
885 	*ppll_ref_div = const_ptr->crtcPLL_M;
887 	*ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);
897 	const struct radeon_tv_mode_constants *const_ptr;
899 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
900 	if (!const_ptr)
903 	*htotal2_cntl = (const_ptr->hor_total & 0x7);
905 	*p2pll_ref_div = const_ptr->crtcPLL_M;
907 	*p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16);