drm/radeon/radeon_legacy_tv.c

242 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
255 	if (tv_dac->tv_std == TV_STD_NTSC ||
256 	    tv_dac->tv_std == TV_STD_NTSC_J ||
257 	    tv_dac->tv_std == TV_STD_PAL_M) {
390 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
395 	WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);
396 	h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);
397 	v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);
400 		tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
402 		if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0)
406 		tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
408 		if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0)
417 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
418 	WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);
419 	WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);
420 	WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);
426 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
441 	if (tv_dac->tv_std == TV_STD_NTSC ||
442 	    tv_dac->tv_std == TV_STD_NTSC_J ||
443 	    tv_dac->tv_std == TV_STD_PAL_M ||
444 	    tv_dac->tv_std == TV_STD_PAL_60)
450 	h_offset = tv_dac->h_pos * H_POS_UNIT;
452 	if (tv_dac->tv_std == TV_STD_NTSC ||
453 	    tv_dac->tv_std == TV_STD_NTSC_J ||
454 	    tv_dac->tv_std == TV_STD_PAL_M) {
466 	h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] ||
467 		     p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]);
469 	tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1;
470 	tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2;
481 	if (tv_dac->tv_std == TV_STD_NTSC ||
482 	    tv_dac->tv_std == TV_STD_NTSC_J ||
483 	    tv_dac->tv_std == TV_STD_PAL_M ||
484 	    tv_dac->tv_std == TV_STD_PAL_60)
485 		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME);
487 		v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME);
492 		  const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart);
494 	tv_dac->tv.hrestart = restart % h_total;
496 	tv_dac->tv.vrestart = restart % v_total;
498 	tv_dac->tv.frestart = restart % f_total;
501 		  (unsigned)tv_dac->tv.frestart,
502 		  (unsigned)tv_dac->tv.vrestart,
503 		  (unsigned)tv_dac->tv.hrestart);
506 	if (tv_dac->tv_std == TV_STD_NTSC ||
507 	    tv_dac->tv_std == TV_STD_NTSC_J ||
508 	    tv_dac->tv_std == TV_STD_PAL_M)
510 			      (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
513 			      (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
515 	tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) |
518 	DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc);
530 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
559 	if (tv_dac->tv_std == TV_STD_NTSC ||
560 	    tv_dac->tv_std == TV_STD_NTSC_J)
569 	if (tv_dac->tv_std == TV_STD_NTSC ||
570 	    tv_dac->tv_std == TV_STD_NTSC_J) {
575 	} else if (tv_dac->tv_std == TV_STD_SCART_PAL) {
604 	if (tv_dac->tv_std == TV_STD_NTSC ||
605 	    tv_dac->tv_std == TV_STD_NTSC_J ||
606 	    tv_dac->tv_std == TV_STD_PAL_M ||
607 	    tv_dac->tv_std == TV_STD_PAL_60)
627 	if (tv_dac->tv_std == TV_STD_NTSC ||
628 	    tv_dac->tv_std == TV_STD_NTSC_J ||
629 	    tv_dac->tv_std == TV_STD_PAL_M ||
630 	    tv_dac->tv_std == TV_STD_PAL_60) {
664 	tv_dac->tv.timing_cntl = tmp;
666 	if (tv_dac->tv_std == TV_STD_NTSC ||
667 	    tv_dac->tv_std == TV_STD_NTSC_J ||
668 	    tv_dac->tv_std == TV_STD_PAL_M ||
669 	    tv_dac->tv_std == TV_STD_PAL_60)
670 		tv_dac_cntl = tv_dac->ntsc_tvdac_adj;
672 		tv_dac_cntl = tv_dac->pal_tvdac_adj;
676 	if (tv_dac->tv_std == TV_STD_NTSC ||
677 	    tv_dac->tv_std == TV_STD_NTSC_J)
682 	if (tv_dac->tv_std == TV_STD_NTSC ||
683 	    tv_dac->tv_std == TV_STD_NTSC_J) {
711 	tv_dac->tv.tv_uv_adr = 0xc8;
713 	if (tv_dac->tv_std == TV_STD_NTSC ||
714 	    tv_dac->tv_std == TV_STD_NTSC_J ||
715 	    tv_dac->tv_std == TV_STD_PAL_M ||
716 	    tv_dac->tv_std == TV_STD_PAL_60) {
727 		tv_dac->tv.h_code_timing[i] = hor_timing[i];
728 		if (tv_dac->tv.h_code_timing[i] == 0)
733 		tv_dac->tv.v_code_timing[i] = vert_timing[i];
734 		if (tv_dac->tv.v_code_timing[i] == 0)
804 	WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);