drm/radeon/radeon_i2c.c

112 				WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
115 				WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
126 		WREG32(rec->mask_clk_reg, temp);
131 	WREG32(rec->a_clk_reg, temp);
134 	WREG32(rec->a_data_reg, temp);
138 	WREG32(rec->en_clk_reg, temp);
141 	WREG32(rec->en_data_reg, temp);
145 	WREG32(rec->mask_clk_reg, temp);
149 	WREG32(rec->mask_data_reg, temp);
164 	WREG32(rec->mask_clk_reg, temp);
168 	WREG32(rec->mask_data_reg, temp);
213 	WREG32(rec->en_clk_reg, val);
226 	WREG32(rec->en_data_reg, val);
347 		WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
461 		WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
465 		WREG32(i2c_data, (p->addr << 1) & 0xff);
466 		WREG32(i2c_data, 0);
467 		WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
471 		WREG32(i2c_cntl_0, reg);
482 				WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
494 				WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
498 				WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
499 				WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
503 				WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
514 						WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
521 				WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
525 				WREG32(i2c_data, (p->addr << 1) & 0xff);
526 				WREG32(i2c_data, p->buf[j]);
527 				WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
531 				WREG32(i2c_cntl_0, reg);
542 						WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
552 	WREG32(i2c_cntl_0, 0);
553 	WREG32(i2c_cntl_1, 0);
554 	WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
562 		WREG32(RADEON_BIOS_6_SCRATCH, tmp);
595 	WREG32(rec->mask_clk_reg, tmp);
600 	WREG32(rec->mask_data_reg, tmp);
606 	WREG32(rec->a_clk_reg, tmp);
611 	WREG32(rec->a_data_reg, tmp);
617 	WREG32(rec->en_clk_reg, tmp);
622 	WREG32(rec->en_data_reg, tmp);
627 	WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
630 	WREG32(0x494, saved2 | 0x1);
632 	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
664 		WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
667 		WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
669 		WREG32(AVIVO_DC_I2C_RESET, 0);
671 		WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
672 		WREG32(AVIVO_DC_I2C_DATA, 0);
674 		WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
675 		WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
678 		WREG32(AVIVO_DC_I2C_CONTROL1, reg);
679 		WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
690 				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
708 				WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
711 				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
713 				WREG32(AVIVO_DC_I2C_RESET, 0);
715 				WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
716 				WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
717 				WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
720 				WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
721 				WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
732 						WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
748 				WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
751 				WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
753 				WREG32(AVIVO_DC_I2C_RESET, 0);
755 				WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
757 					WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
759 				WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
760 				WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
763 				WREG32(AVIVO_DC_I2C_CONTROL1, reg);
764 				WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
775 						WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
787 	WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
790 	WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
792 	WREG32(AVIVO_DC_I2C_RESET, 0);
794 	WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
795 	WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
796 	WREG32(0x494, saved2);
799 	WREG32(RADEON_BIOS_6_SCRATCH, tmp);