Lines Matching defs:lvds

1088 	struct radeon_encoder_lvds *lvds;
1093 	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1095 	if (!lvds)
1102 	lvds->panel_pwr_delay = 200;
1103 	lvds->panel_vcc_delay = 2000;
1105 	lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1106 	lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1107 	lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1110 		lvds->native_mode.vdisplay =
1114 		lvds->native_mode.vdisplay =
1118 		lvds->native_mode.hdisplay =
1122 		lvds->native_mode.hdisplay =
1125 	if ((lvds->native_mode.hdisplay < 640) ||
1126 	    (lvds->native_mode.vdisplay < 480)) {
1127 		lvds->native_mode.hdisplay = 640;
1128 		lvds->native_mode.vdisplay = 480;
1134 		lvds->use_bios_dividers = false;
1136 		lvds->panel_ref_divider =
1138 		lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1139 		lvds->panel_fb_divider = ppll_val & 0x7ff;
1141 		if ((lvds->panel_ref_divider != 0) &&
1142 		    (lvds->panel_fb_divider > 3))
1143 			lvds->use_bios_dividers = true;
1145 	lvds->panel_vcc_delay = 200;
1148 	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1149 		 lvds->native_mode.vdisplay);
1151 	return lvds;
1163 	struct radeon_encoder_lvds *lvds = NULL;
1168 		lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1170 		if (!lvds)
1179 		lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1180 		lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1182 		DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1183 			 lvds->native_mode.vdisplay);
1185 		lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1186 		lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1188 		lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1189 		lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1190 		lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1192 		lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1193 		lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1194 		lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1195 		if ((lvds->panel_ref_divider != 0) &&
1196 		    (lvds->panel_fb_divider > 3))
1197 			lvds->use_bios_dividers = true;
1200 		lvds->lvds_gen_cntl = 0xff00;
1202 			lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1205 			lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1209 			lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1212 			lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1215 			lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1222 			lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1225 			lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1228 			lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1231 			lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1233 		lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1240 			if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1241 			    (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1244 				if (hss > lvds->native_mode.hdisplay)
1247 				lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1249 				lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1251 				lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1254 				lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1256 				lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1258 				lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1261 				lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1262 				lvds->native_mode.flags = 0;
1264 				drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1270 		lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1273 	if (lvds)
1274 		encoder->native_mode = lvds->native_mode;
1275 	return lvds;