drm/radeon/radeon_bios.c

266 	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
269 		WREG32(AVIVO_D1VGA_CONTROL,
272 		WREG32(AVIVO_D2VGA_CONTROL,
275 		WREG32(AVIVO_VGA_RENDER_CONTROL,
278 	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
283 	WREG32(R600_BUS_CNTL, bus_cntl);
285 		WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
286 		WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
287 		WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
289 	WREG32(R600_ROM_CNTL, rom_cntl);
313 	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
315 	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
317 	WREG32(AVIVO_D1VGA_CONTROL,
320 	WREG32(AVIVO_D2VGA_CONTROL,
323 	WREG32(AVIVO_VGA_RENDER_CONTROL,
330 		WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
338 		WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
340 		WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
346 		WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
353 	WREG32(RADEON_VIPH_CONTROL, viph_control);
354 	WREG32(R600_BUS_CNTL, bus_cntl);
355 	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
356 	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
357 	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
358 	WREG32(R600_ROM_CNTL, rom_cntl);
392 	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
394 	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
396 	WREG32(AVIVO_D1VGA_CONTROL,
399 	WREG32(AVIVO_D2VGA_CONTROL,
402 	WREG32(AVIVO_VGA_RENDER_CONTROL,
405 	WREG32(R600_ROM_CNTL,
410 	WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
411 	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
413 	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
415 	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
417 	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
419 	WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
424 	WREG32(RADEON_VIPH_CONTROL, viph_control);
425 	WREG32(R600_BUS_CNTL, bus_cntl);
426 	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
427 	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
428 	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
429 	WREG32(R600_ROM_CNTL, rom_cntl);
430 	WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
431 	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
432 	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
433 	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
434 	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
435 	WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
462 	WREG32(RADEON_SEPROM_CNTL1,
465 	WREG32(RADEON_GPIOPAD_A, 0);
466 	WREG32(RADEON_GPIOPAD_EN, 0);
467 	WREG32(RADEON_GPIOPAD_MASK, 0);
470 	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
473 	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
476 	WREG32(AVIVO_D1VGA_CONTROL,
479 	WREG32(AVIVO_D2VGA_CONTROL,
482 	WREG32(AVIVO_VGA_RENDER_CONTROL,
488 	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
489 	WREG32(RADEON_VIPH_CONTROL, viph_control);
490 	WREG32(RV370_BUS_CNTL, bus_cntl);
491 	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
492 	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
493 	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
494 	WREG32(RADEON_GPIOPAD_A, gpiopad_a);
495 	WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
496 	WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
530 	WREG32(RADEON_SEPROM_CNTL1,
535 	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
539 		WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
541 		WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
544 	WREG32(RADEON_CRTC_GEN_CNTL,
549 		WREG32(RADEON_CRTC2_GEN_CNTL,
554 	WREG32(RADEON_CRTC_EXT_CNTL,
560 		WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
566 	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
567 	WREG32(RADEON_VIPH_CONTROL, viph_control);
569 		WREG32(RV370_BUS_CNTL, bus_cntl);
571 		WREG32(RADEON_BUS_CNTL, bus_cntl);
572 	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
574 		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
576 	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
578 		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);