drm/radeon/radeon_atombios.c

1627 	struct radeon_encoder_atom_dig *lvds = NULL;
1634 		lvds =
1637 		if (!lvds)
1640 		lvds->native_mode.clock =
1642 		lvds->native_mode.hdisplay =
1644 		lvds->native_mode.vdisplay =
1646 		lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1648 		lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1650 		lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1652 		lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1654 		lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1656 		lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1658 		lvds->panel_pwr_delay =
1660 		lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1664 			lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1666 			lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1668 			lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1670 			lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1672 			lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1674 		lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1675 		lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1678 		drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1680 		lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1682 		encoder->native_mode = lvds->native_mode;
1685 			lvds->linkb = true;
1687 			lvds->linkb = false;
1741 					lvds->native_mode.width_mm = panel_res_record->usHSize;
1742 					lvds->native_mode.height_mm = panel_res_record->usVSize;
1755 	return lvds;