Lines Matching refs:WREG32
53 WREG32(TN_SMC_IND_INDEX_0, (reg));
64 WREG32(TN_SMC_IND_INDEX_0, (reg));
65 WREG32(TN_SMC_IND_DATA_0, (v));
657 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
658 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
662 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
663 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
668 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
671 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
672 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
673 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
980 WREG32((0x2c14 + j), 0x00000000);
981 WREG32((0x2c18 + j), 0x00000000);
982 WREG32((0x2c1c + j), 0x00000000);
983 WREG32((0x2c20 + j), 0x00000000);
984 WREG32((0x2c24 + j), 0x00000000);
987 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
988 WREG32(SRBM_INT_CNTL, 0x1);
989 WREG32(SRBM_INT_ACK, 0x1);
1069 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1070 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1089 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1090 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1098 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1099 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1101 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1102 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1104 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1105 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1106 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1107 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1108 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1109 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1110 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1129 WREG32(GB_BACKEND_MAP, tmp);
1134 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1135 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1136 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1137 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1142 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1143 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1146 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1150 WREG32(SX_DEBUG_1, sx_debug_1);
1155 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1157 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1160 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1161 WREG32(SQ_LSTMP_RING_BASE, 0);
1162 WREG32(SQ_HSTMP_RING_BASE, 0);
1163 WREG32(SQ_ESTMP_RING_BASE, 0);
1164 WREG32(SQ_GSTMP_RING_BASE, 0);
1165 WREG32(SQ_VSTMP_RING_BASE, 0);
1166 WREG32(SQ_PSTMP_RING_BASE, 0);
1168 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1170 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1174 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1179 WREG32(VGT_NUM_INSTANCES, 1);
1181 WREG32(CP_PERFMON_CNTL, 0);
1183 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1188 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1189 WREG32(SQ_CONFIG, (VC_ENABLE |
1194 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1196 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1199 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1202 WREG32(VGT_GS_VERTEX_REUSE, 16);
1203 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1205 WREG32(CB_PERF_CTR0_SEL_0, 0);
1206 WREG32(CB_PERF_CTR0_SEL_1, 0);
1207 WREG32(CB_PERF_CTR1_SEL_0, 0);
1208 WREG32(CB_PERF_CTR1_SEL_1, 0);
1209 WREG32(CB_PERF_CTR2_SEL_0, 0);
1210 WREG32(CB_PERF_CTR2_SEL_1, 0);
1211 WREG32(CB_PERF_CTR3_SEL_0, 0);
1212 WREG32(CB_PERF_CTR3_SEL_1, 0);
1216 WREG32(HDP_MISC_CNTL, tmp);
1219 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1221 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1242 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1245 WREG32(VM_INVALIDATE_REQUEST, 1);
1260 WREG32(MC_VM_MX_L1_TLB_CNTL,
1268 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1274 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1275 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1279 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1280 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1281 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1282 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1284 WREG32(VM_CONTEXT0_CNTL2, 0);
1285 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1288 WREG32(0x15D4, 0);
1289 WREG32(0x15D8, 0);
1290 WREG32(0x15DC, 0);
1298 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1299 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),
1301 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1306 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1308 WREG32(VM_CONTEXT1_CNTL2, 4);
1309 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1342 WREG32(VM_CONTEXT0_CNTL, 0);
1343 WREG32(VM_CONTEXT1_CNTL, 0);
1345 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1349 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1353 WREG32(VM_L2_CNTL2, 0);
1354 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1369 WREG32(SRBM_GFX_CNTL, RINGID(ring));
1370 WREG32(CP_INT_CNTL, cp_int_cntl);
1438 WREG32(CP_ME_CNTL, 0);
1442 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1443 WREG32(SCRATCH_UMSK, 0);
1486 WREG32(CP_RB0_WPTR, ring->wptr);
1489 WREG32(CP_RB1_WPTR, ring->wptr);
1492 WREG32(CP_RB2_WPTR, ring->wptr);
1508 WREG32(CP_PFP_UCODE_ADDR, 0);
1510 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1511 WREG32(CP_PFP_UCODE_ADDR, 0);
1514 WREG32(CP_ME_RAM_WADDR, 0);
1516 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1518 WREG32(CP_PFP_UCODE_ADDR, 0);
1519 WREG32(CP_ME_RAM_WADDR, 0);
1520 WREG32(CP_ME_RAM_RADDR, 0);
1639 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1647 WREG32(GRBM_SOFT_RESET, 0);
1650 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1651 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1654 WREG32(CP_RB_WPTR_DELAY, 0);
1656 WREG32(CP_DEBUG, (1 << 27));
1659 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1660 WREG32(SCRATCH_UMSK, 0xff);
1673 WREG32(cp_rb_cntl[i], rb_cntl);
1677 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1678 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1684 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1693 WREG32(cp_rb_rptr[i], 0);
1694 WREG32(cp_rb_wptr[i], ring->wptr);
1820 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1826 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1833 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1897 WREG32(GRBM_SOFT_RESET, tmp);
1903 WREG32(GRBM_SOFT_RESET, tmp);
1911 WREG32(SRBM_SOFT_RESET, tmp);
1917 WREG32(SRBM_SOFT_RESET, tmp);