Lines Matching defs:table
560 struct radeon_clock_voltage_dependency_table *table =
563 if (table && table->count) {
565 if (table->entries[i].clk == pi->boot_pl.sclk)
572 struct sumo_sclk_voltage_mapping_table *table =
575 if (table->num_max_dpm_entries == 0)
579 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
662 struct radeon_uvd_clock_voltage_dependency_table *table =
668 if (table == NULL || table->count == 0)
672 for (i = 0; i < table->count; i++) {
674 (pi->high_voltage_t < table->entries[i].v))
677 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
678 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
679 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
682 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
684 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
687 table->entries[i].vclk, false, ÷rs);
693 table->entries[i].dclk, false, ÷rs);
735 struct radeon_vce_clock_voltage_dependency_table *table =
739 if (table == NULL || table->count == 0)
743 for (i = 0; i < table->count; i++) {
745 pi->high_voltage_t < table->entries[i].v)
748 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
749 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
752 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
755 table->entries[i].evclk, false, ÷rs);
796 struct radeon_clock_voltage_dependency_table *table =
802 if (table == NULL || table->count == 0)
806 for (i = 0; i < table->count; i++) {
808 pi->high_voltage_t < table->entries[i].v)
811 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
812 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
815 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
818 table->entries[i].clk, false, ÷rs);
862 struct radeon_clock_voltage_dependency_table *table =
868 if (table == NULL || table->count == 0)
872 for (i = 0; i < table->count; i++) {
873 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
874 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
877 table->entries[i].clk, false, ÷rs);
921 struct radeon_clock_voltage_dependency_table *table =
924 if (table && table->count) {
927 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
929 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
931 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
933 else if (kv_get_clock_difference(table->entries[i].clk, 20000) < 200)
935 else if (kv_get_clock_difference(table->entries[i].clk, 10000) < 200)
944 struct sumo_sclk_voltage_mapping_table *table =
948 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
950 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
952 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
954 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
956 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1246 struct radeon_uvd_clock_voltage_dependency_table *table =
1252 if (table->count)
1253 pi->uvd_boot_level = table->count - 1;
1282 struct radeon_vce_clock_voltage_dependency_table *table =
1285 for (i = 0; i < table->count; i++) {
1286 if (table->entries[i].evclk >= evclk)
1298 struct radeon_vce_clock_voltage_dependency_table *table =
1307 pi->vce_boot_level = table->count - 1;
1339 struct radeon_clock_voltage_dependency_table *table =
1345 pi->samu_boot_level = table->count - 1;
1370 struct radeon_clock_voltage_dependency_table *table =
1373 for (i = 0; i < table->count; i++) {
1374 if (table->entries[i].clk >= 0) /* XXX */
1378 if (i >= table->count)
1379 i = table->count - 1;
1403 struct radeon_clock_voltage_dependency_table *table =
1409 pi->acp_boot_level = table->count - 1;
1531 struct radeon_clock_voltage_dependency_table *table =
1534 if (table && table->count) {
1536 if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1544 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1550 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1551 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1557 struct sumo_sclk_voltage_mapping_table *table =
1561 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1569 if (table->entries[i].sclk_frequency <=
1577 table->entries[pi->highest_valid].sclk_frequency) >
1578 (table->entries[pi->lowest_valid].sclk_frequency -
1764 struct radeon_clock_and_voltage_limits *table)
1770 table->sclk =
1772 table->vddc =
1777 table->mclk = pi->sys_info.nbp_memory_clock[0];
1903 struct radeon_clock_voltage_dependency_table *table =
1907 if (table && table->count) {
1908 for (i = table->count - 1; i >= 0; i--) {
1910 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
1917 struct sumo_sclk_voltage_mapping_table *table =
1920 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
1922 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
1944 struct radeon_clock_voltage_dependency_table *table =
1964 for (i = table->count - 1; i >= 0; i--) {
1965 if (stable_p_state_sclk >= table->entries[i].clk) {
1966 stable_p_state_sclk = table->entries[i].clk;
1972 stable_p_state_sclk = table->entries[0].clk;
1989 if (table && table->count) {
1995 ps->levels[i].sclk = table->entries[limit].clk;
1999 struct sumo_sclk_voltage_mapping_table *table =
2007 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2148 struct radeon_clock_voltage_dependency_table *table =
2151 if (table && table->count) {
2155 for (i = 0; i < table->count; i++) {
2158 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2161 kv_set_divider_value(rdev, i, table->entries[i].clk);
2164 table->entries[i].v);
2171 struct sumo_sclk_voltage_mapping_table *table =
2175 for (i = 0; i < table->num_max_dpm_entries; i++) {
2178 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2181 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2182 kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2301 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);