Lines Matching refs:WREG32
63 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
74 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
75 WREG32(EVERGREEN_CG_IND_DATA, (v));
85 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
96 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
97 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
107 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
118 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
119 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
1184 WREG32(CG_SCRATCH1, cg_scratch);
1345 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
1423 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
1426 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,
1429 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1431 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1687 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
1712 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
1789 WREG32(DC_HPDx_CONTROL(hpd), tmp);
1818 WREG32(DC_HPDx_CONTROL(hpd), 0);
1870 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
1873 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
2291 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2292 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
2299 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2300 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
2304 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
2307 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2308 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2382 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2384 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
2413 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
2416 WREG32(VM_L2_CNTL2, 0);
2417 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2424 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
2425 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
2426 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
2428 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
2429 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
2430 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
2435 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
2437 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
2438 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
2439 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
2440 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
2441 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2442 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2443 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2444 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2446 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2448 WREG32(VM_CONTEXT1_CNTL, 0);
2463 WREG32(VM_CONTEXT0_CNTL, 0);
2464 WREG32(VM_CONTEXT1_CNTL, 0);
2467 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
2469 WREG32(VM_L2_CNTL2, 0);
2470 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2473 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
2474 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
2475 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
2476 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
2477 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
2478 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
2479 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
2496 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
2499 WREG32(VM_L2_CNTL2, 0);
2500 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2506 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
2507 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
2508 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
2509 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
2510 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
2511 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
2512 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
2513 WREG32(VM_CONTEXT0_CNTL, 0);
2514 WREG32(VM_CONTEXT1_CNTL, 0);
2643 WREG32(EVERGREEN_DP_VID_STREAM_CNTL +
2659 WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl);
2674 WREG32(VGA_RENDER_CONTROL, 0);
2685 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2687 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
2688 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2694 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2696 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2697 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2719 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2722 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2723 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2736 WREG32(BIF_FB_EN, 0);
2739 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
2750 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2755 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2768 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
2770 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
2772 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
2774 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
2779 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
2780 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
2789 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
2794 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2799 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2813 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
2815 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
2822 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2823 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
2824 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2828 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2829 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2830 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2843 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
2845 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
2857 WREG32((0x2c14 + j), 0x00000000);
2858 WREG32((0x2c18 + j), 0x00000000);
2859 WREG32((0x2c1c + j), 0x00000000);
2860 WREG32((0x2c20 + j), 0x00000000);
2861 WREG32((0x2c24 + j), 0x00000000);
2863 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2870 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2875 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2877 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2881 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2883 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2887 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2889 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2892 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
2900 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
2904 WREG32(MC_VM_FB_LOCATION, tmp);
2905 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2906 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2907 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2909 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
2910 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
2911 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
2913 WREG32(MC_VM_AGP_BASE, 0);
2914 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2915 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2973 WREG32(CP_RB_CNTL,
2980 WREG32(CP_PFP_UCODE_ADDR, 0);
2982 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
2983 WREG32(CP_PFP_UCODE_ADDR, 0);
2986 WREG32(CP_ME_RAM_WADDR, 0);
2988 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
2990 WREG32(CP_PFP_UCODE_ADDR, 0);
2991 WREG32(CP_ME_RAM_WADDR, 0);
2992 WREG32(CP_ME_RAM_RADDR, 0);
3017 WREG32(CP_ME_CNTL, cp_me);
3070 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
3078 WREG32(GRBM_SOFT_RESET, 0);
3087 WREG32(CP_RB_CNTL, tmp);
3088 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3089 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3092 WREG32(CP_RB_WPTR_DELAY, 0);
3095 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
3096 WREG32(CP_RB_RPTR_WR, 0);
3098 WREG32(CP_RB_WPTR, ring->wptr);
3101 WREG32(CP_RB_RPTR_ADDR,
3103 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
3104 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3107 WREG32(SCRATCH_UMSK, 0xff);
3110 WREG32(SCRATCH_UMSK, 0);
3114 WREG32(CP_RB_CNTL, tmp);
3116 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3117 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
3386 WREG32((0x2c14 + j), 0x00000000);
3387 WREG32((0x2c18 + j), 0x00000000);
3388 WREG32((0x2c1c + j), 0x00000000);
3389 WREG32((0x2c20 + j), 0x00000000);
3390 WREG32((0x2c24 + j), 0x00000000);
3393 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3394 WREG32(SRBM_INT_CNTL, 0x1);
3395 WREG32(SRBM_INT_ACK, 0x1);
3464 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
3465 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
3485 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
3486 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
3494 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
3495 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
3497 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3498 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
3499 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3500 WREG32(DMA_TILING_CONFIG, gb_addr_config);
3501 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3502 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3503 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3520 WREG32(GB_BACKEND_MAP, tmp);
3522 WREG32(CGTS_SYS_TCC_DISABLE, 0);
3523 WREG32(CGTS_TCC_DISABLE, 0);
3524 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
3525 WREG32(CGTS_USER_TCC_DISABLE, 0);
3528 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
3531 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
3533 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
3540 WREG32(SX_DEBUG_1, sx_debug_1);
3546 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
3549 WREG32(SMX_SAR_CTL0, 0x00010000);
3551 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
3555 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
3559 WREG32(VGT_NUM_INSTANCES, 1);
3560 WREG32(SPI_CONFIG_CNTL, 0);
3561 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3562 WREG32(CP_PERFMON_CNTL, 0);
3564 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
3630 WREG32(SQ_CONFIG, sq_config);
3631 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
3632 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
3633 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
3634 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
3635 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
3636 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
3637 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
3638 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
3639 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
3640 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
3642 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3658 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
3660 WREG32(VGT_GS_VERTEX_REUSE, 16);
3661 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
3662 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3664 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
3665 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
3667 WREG32(CB_PERF_CTR0_SEL_0, 0);
3668 WREG32(CB_PERF_CTR0_SEL_1, 0);
3669 WREG32(CB_PERF_CTR1_SEL_0, 0);
3670 WREG32(CB_PERF_CTR1_SEL_1, 0);
3671 WREG32(CB_PERF_CTR2_SEL_0, 0);
3672 WREG32(CB_PERF_CTR2_SEL_1, 0);
3673 WREG32(CB_PERF_CTR3_SEL_0, 0);
3674 WREG32(CB_PERF_CTR3_SEL_1, 0);
3677 WREG32(CB_COLOR0_BASE, 0);
3678 WREG32(CB_COLOR1_BASE, 0);
3679 WREG32(CB_COLOR2_BASE, 0);
3680 WREG32(CB_COLOR3_BASE, 0);
3681 WREG32(CB_COLOR4_BASE, 0);
3682 WREG32(CB_COLOR5_BASE, 0);
3683 WREG32(CB_COLOR6_BASE, 0);
3684 WREG32(CB_COLOR7_BASE, 0);
3685 WREG32(CB_COLOR8_BASE, 0);
3686 WREG32(CB_COLOR9_BASE, 0);
3687 WREG32(CB_COLOR10_BASE, 0);
3688 WREG32(CB_COLOR11_BASE, 0);
3692 WREG32(i, 0);
3694 WREG32(i, 0);
3698 WREG32(HDP_MISC_CNTL, tmp);
3701 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3703 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3908 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
3914 WREG32(DMA_RB_CNTL, tmp);
3975 WREG32(GRBM_SOFT_RESET, tmp);
3981 WREG32(GRBM_SOFT_RESET, tmp);
3989 WREG32(SRBM_SOFT_RESET, tmp);
3995 WREG32(SRBM_SOFT_RESET, tmp);
4018 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
4023 WREG32(DMA_RB_CNTL, tmp);
4377 WREG32(RLC_CNTL, mask);
4390 WREG32(RLC_HB_CNTL, 0);
4401 WREG32(TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK, always_on_bitmap);
4402 WREG32(TN_RLC_LB_PARAMS, 0x00601004);
4403 WREG32(TN_RLC_LB_INIT_SIMD_MASK, 0xffffffff);
4404 WREG32(TN_RLC_LB_CNTR_INIT, 0x00000000);
4405 WREG32(TN_RLC_LB_CNTR_MAX, 0x00002000);
4408 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
4409 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
4411 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
4412 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
4414 WREG32(RLC_HB_BASE, 0);
4415 WREG32(RLC_HB_RPTR, 0);
4416 WREG32(RLC_HB_WPTR, 0);
4417 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
4418 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
4420 WREG32(RLC_MC_CNTL, 0);
4421 WREG32(RLC_UCODE_CNTL, 0);
4426 WREG32(RLC_UCODE_ADDR, i);
4427 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
4431 WREG32(RLC_UCODE_ADDR, i);
4432 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
4436 WREG32(RLC_UCODE_ADDR, i);
4437 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
4440 WREG32(RLC_UCODE_ADDR, 0);
4468 WREG32(CAYMAN_DMA1_CNTL, tmp);
4470 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4472 WREG32(DMA_CNTL, tmp);
4473 WREG32(GRBM_INT_CNTL, 0);
4474 WREG32(SRBM_INT_CNTL, 0);
4476 WREG32(INT_MASK + crtc_offsets[i], 0);
4478 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
4482 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
4483 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
4565 WREG32(CP_INT_CNTL, cp_int_cntl);
4567 WREG32(DMA_CNTL, dma_cntl);
4570 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
4572 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
4583 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
4593 WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int);
4595 WREG32(CG_THERMAL_INT, thermal_int);
4629 WREG32(GRPH_INT_STATUS + crtc_offsets[j],
4635 WREG32(VBLANK_STATUS + crtc_offsets[j],
4638 WREG32(VLINE_STATUS + crtc_offsets[j],
4695 WREG32(IH_RB_CNTL, tmp);
4836 WREG32(SRBM_INT_ACK, 0x1);
4911 WREG32(IH_RB_RPTR, rptr);