Lines Matching defs:dsi_ctx
37 void (*init_func)(struct s6d7aa0 *ctx, struct mipi_dsi_multi_context *dsi_ctx);
38 void (*off_func)(struct mipi_dsi_multi_context *dsi_ctx);
65 static void s6d7aa0_lock(struct s6d7aa0 *ctx, struct mipi_dsi_multi_context *dsi_ctx, bool lock)
68 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD1, 0xa5, 0xa5);
69 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD2, 0xa5, 0xa5);
71 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD3, 0x5a, 0x5a);
73 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD1, 0x5a, 0x5a);
74 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD2, 0x5a, 0x5a);
76 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD3, 0xa5, 0xa5);
83 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
85 ctx->desc->init_func(ctx, &dsi_ctx);
87 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
89 return dsi_ctx.accum_err;
95 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
97 ctx->desc->off_func(&dsi_ctx);
99 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
100 mipi_dsi_msleep(&dsi_ctx, 64);
102 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
104 mipi_dsi_msleep(&dsi_ctx, 120);
152 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
154 mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, brightness);
156 return dsi_ctx.accum_err;
193 static void s6d7aa0_lsl080al02_init(struct s6d7aa0 *ctx, struct mipi_dsi_multi_context *dsi_ctx)
195 mipi_dsi_usleep_range(dsi_ctx, 20000, 25000);
197 s6d7aa0_lock(ctx, dsi_ctx, false);
199 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_OTP_RELOAD, 0x00, 0x10);
200 mipi_dsi_usleep_range(dsi_ctx, 1000, 1500);
203 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb6, 0x10);
206 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BL_CTL, 0x40, 0x00, 0x28);
208 mipi_dsi_usleep_range(dsi_ctx, 5000, 6000);
210 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x04);
212 mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx);
214 mipi_dsi_msleep(dsi_ctx, 120);
215 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
217 s6d7aa0_lock(ctx, dsi_ctx, true);
219 mipi_dsi_dcs_set_display_on_multi(dsi_ctx);
222 static void s6d7aa0_lsl080al02_off(struct mipi_dsi_multi_context *dsi_ctx)
225 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BL_CTL, 0x40, 0x00, 0x20);
256 static void s6d7aa0_lsl080al03_init(struct s6d7aa0 *ctx, struct mipi_dsi_multi_context *dsi_ctx)
258 mipi_dsi_usleep_range(dsi_ctx, 20000, 25000);
260 s6d7aa0_lock(ctx, dsi_ctx, false);
263 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BL_CTL, 0xc7, 0x00, 0x29);
264 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbc, 0x01, 0x4e, 0xa0);
265 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfd, 0x16, 0x10, 0x11, 0x23,
267 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfe, 0x00, 0x02, 0x03, 0x21,
270 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BL_CTL, 0x40, 0x00, 0x08);
271 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbc, 0x01, 0x4e, 0x0b);
272 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfd, 0x16, 0x10, 0x11, 0x23,
274 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xfe, 0x00, 0x02, 0x03, 0x21,
278 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb3, 0x51);
279 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
280 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xf2, 0x02, 0x08, 0x08);
282 mipi_dsi_usleep_range(dsi_ctx, 10000, 11000);
284 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc0, 0x80, 0x80, 0x30);
285 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xcd,
288 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xce,
291 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc1, 0x03);
293 mipi_dsi_dcs_exit_sleep_mode_multi(dsi_ctx);
294 s6d7aa0_lock(ctx, dsi_ctx, true);
295 mipi_dsi_dcs_set_display_on_multi(dsi_ctx);
298 static void s6d7aa0_lsl080al03_off(struct mipi_dsi_multi_context *dsi_ctx)
300 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x22, 0x00);