Lines Matching defs:dsi_ctx

51 #define novatek_nt37801_switch_page(dsi_ctx, page) \
52 	mipi_dsi_dcs_write_seq_multi((dsi_ctx), NT37801_DCS_SWITCH_PAGE, \
58 	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
62 	novatek_nt37801_switch_page(&dsi_ctx, 0x01);
63 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x01);
64 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc5, 0x0b, 0x0b, 0x0b);
65 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80);
66 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02);
67 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf5, 0x10);
68 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x1b);
69 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4, 0x55);
70 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x18);
71 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf8, 0x19);
72 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0f);
73 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfc, 0x00);
74 	mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 0x059f);
75 	mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 0x0c7f);
76 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x03, 0x03);
77 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x91,
81 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x81);
82 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x23);
83 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb,
87 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x06);
88 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0xdc);
89 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_GAMMA_CURVE, 0x00);
90 	mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
91 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x00, 0x18, 0x00, 0x10);
92 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY,
94 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51,
96 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x01);
97 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00);
98 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9c, 0x01);
99 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_MEMORY_START);
100 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);
102 	novatek_nt37801_switch_page(&dsi_ctx, 0x01);
103 	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x55, 0x01, 0xff, 0x03);
104 	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
105 	mipi_dsi_msleep(&dsi_ctx, 120);
106 	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
107 	mipi_dsi_msleep(&dsi_ctx, 20);
109 	return dsi_ctx.accum_err;
115 	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
119 	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
120 	mipi_dsi_msleep(&dsi_ctx, 20);
122 	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
123 	mipi_dsi_msleep(&dsi_ctx, 120);
125 	return dsi_ctx.accum_err;