subdev/gsp/fwsec.c

27 #include <nvfw/fw.h>
89 nvkm_gsp_fwsec_patch(struct nvkm_gsp *gsp, struct nvkm_falcon_fw *fw, u32 if_offset, u32 init_cmd)
91 	union nvfw_falcon_appif_hdr *hdr = (void *)(fw->fw.img + fw->dmem_base_img + if_offset);
92 	const u8 *dmem = fw->fw.img + fw->dmem_base_img;
174 		  struct nvkm_falcon_fw *fw)
185 				  &gsp->falcon, fw);
189 	fw->nmem_base_img = 0;
190 	fw->nmem_base = desc->IMEMPhysBase;
191 	fw->nmem_size = desc->IMEMLoadSize - desc->IMEMSecSize;
193 	fw->imem_base_img = 0;
194 	fw->imem_base = desc->IMEMSecBase;
195 	fw->imem_size = desc->IMEMSecSize;
197 	fw->dmem_base_img = desc->DMEMOffset;
198 	fw->dmem_base = desc->DMEMPhysBase;
199 	fw->dmem_size = desc->DMEMLoadSize;
209 	fw->boot_addr = bld->start_tag << 8;
210 	fw->boot_size = bld->code_size;
211 	fw->boot = kmemdup(bl->data + hdr->data_offset + bld->code_off, fw->boot_size, GFP_KERNEL);
212 	if (!fw->boot)
218 	return nvkm_gsp_fwsec_patch(gsp, fw, desc->InterfaceOffset, init_cmd);
224 		  struct nvkm_falcon_fw *fw)
233 				  &gsp->falcon, fw);
237 	fw->imem_base_img = 0;
238 	fw->imem_base = desc->IMEMPhysBase;
239 	fw->imem_size = desc->IMEMLoadSize;
240 	fw->dmem_base_img = desc->IMEMLoadSize;
241 	fw->dmem_base = desc->DMEMPhysBase;
242 	fw->dmem_size = ALIGN(desc->DMEMLoadSize, 256);
243 	fw->dmem_sign = desc->PKCDataOffset;
244 	fw->boot_addr = 0;
245 	fw->fuse_ver = desc->SignatureVersions;
246 	fw->ucode_id = desc->UcodeId;
247 	fw->engine_id = desc->EngineIdMask;
250 	ret = nvkm_falcon_fw_sign(fw, fw->dmem_base_img + desc->PKCDataOffset, 96 * 4,
257 	return nvkm_gsp_fwsec_patch(gsp, fw, desc->InterfaceOffset, init_cmd);
271 	struct nvkm_falcon_fw fw = {};
293 	case 2: ret = nvkm_gsp_fwsec_v2(gsp, name, &desc->v2, size, init_cmd, &fw); break;
294 	case 3: ret = nvkm_gsp_fwsec_v3(gsp, name, &desc->v3, size, init_cmd, &fw); break;
306 	ret = nvkm_falcon_fw_boot(&fw, subdev, true, &mbox0, NULL, 0, 0);
307 	nvkm_falcon_fw_dtor(&fw);