subdev/clk/nv50.c

36 	case 0x50: /* it exists, but only has bit 31, not the dividers.. */
37 	case 0x84:
38 	case 0x86:
39 	case 0x98:
40 	case 0xa0:
41 		return nvkm_rd32(device, 0x004700);
42 	case 0x92:
43 	case 0x94:
44 	case 0x96:
45 		return nvkm_rd32(device, 0x004800);
47 		return 0x00000000;
57 	u32 rsel = nvkm_rd32(device, 0x00e18c);
61 	case 0x50:
62 	case 0xa0:
64 		case 0x4020:
65 		case 0x4028: id = !!(rsel & 0x00000004); break;
66 		case 0x4008: id = !!(rsel & 0x00000008); break;
67 		case 0x4030: id = 0; break;
70 			return 0;
73 		coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c));
74 		ref *=  (coef & 0x01000000) ? 2 : 4;
75 		P    =  (coef & 0x00070000) >> 16;
76 		N    = ((coef & 0x0000ff00) >> 8) + 1;
77 		M    = ((coef & 0x000000ff) >> 0) + 1;
79 	case 0x84:
80 	case 0x86:
81 	case 0x92:
82 		coef = nvkm_rd32(device, 0x00e81c);
83 		P    = (coef & 0x00070000) >> 16;
84 		N    = (coef & 0x0000ff00) >> 8;
85 		M    = (coef & 0x000000ff) >> 0;
87 	case 0x94:
88 	case 0x96:
89 	case 0x98:
90 		rsel = nvkm_rd32(device, 0x00c050);
92 		case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
93 		case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
94 		case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
95 		case 0x4030: rsel = 3; break;
98 			return 0;
102 		case 0: id = 1; break;
105 		case 3: id = 0; break;
108 		coef =  nvkm_rd32(device, 0x00e81c + (id * 0x28));
109 		P    = (nvkm_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7;
110 		P   += (coef & 0x00070000) >> 16;
111 		N    = (coef & 0x0000ff00) >> 8;
112 		M    = (coef & 0x000000ff) >> 0;
121 	return 0;
129 	u32 src, mast = nvkm_rd32(device, 0x00c040);
132 	case 0x004028:
133 		src = !!(mast & 0x00200000);
135 	case 0x004020:
136 		src = !!(mast & 0x00400000);
138 	case 0x004008:
139 		src = !!(mast & 0x00010000);
141 	case 0x004030:
142 		src = !!(mast & 0x02000000);
144 	case 0x00e810:
148 		return 0;
161 	u32 mast = nvkm_rd32(device, 0x00c040);
162 	u32 ctrl = nvkm_rd32(device, base + 0);
165 	u32 freq = 0;
168 	if (base == 0x004028 && (mast & 0x00100000)) {
170 		if (device->chipset != 0xa0)
174 	N2 = (coef & 0xff000000) >> 24;
175 	M2 = (coef & 0x00ff0000) >> 16;
176 	N1 = (coef & 0x0000ff00) >> 8;
177 	M1 = (coef & 0x000000ff);
178 	if ((ctrl & 0x80000000) && M1) {
180 		if ((ctrl & 0x40000100) == 0x40000000) {
184 				freq = 0;
197 	u32 mast = nvkm_rd32(device, 0x00c040);
198 	u32 P = 0;
212 		switch (mast & 0x30000000) {
213 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
214 		case 0x10000000: break;
215 		case 0x20000000: /* !0x50 */
216 		case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);
220 		if (!(mast & 0x00100000))
221 			P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16;
222 		switch (mast & 0x00000003) {
223 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
224 		case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6);
225 		case 0x00000002: return read_pll(clk, 0x004020) >> P;
226 		case 0x00000003: return read_pll(clk, 0x004028) >> P;
230 		P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16;
231 		switch (mast & 0x00000030) {
232 		case 0x00000000:
233 			if (mast & 0x00000080)
236 		case 0x00000010: break;
237 		case 0x00000020: return read_pll(clk, 0x004028) >> P;
238 		case 0x00000030: return read_pll(clk, 0x004020) >> P;
242 		P = (nvkm_rd32(device, 0x004008) & 0x00070000) >> 16;
243 		if (nvkm_rd32(device, 0x004008) & 0x00000200) {
244 			switch (mast & 0x0000c000) {
245 			case 0x00000000:
247 			case 0x00008000:
248 			case 0x0000c000:
252 			return read_pll(clk, 0x004008) >> P;
256 		P = (read_div(clk) & 0x00000700) >> 8;
258 		case 0x84:
259 		case 0x86:
260 		case 0x92:
261 		case 0x94:
262 		case 0x96:
263 		case 0xa0:
264 			switch (mast & 0x00000c00) {
265 			case 0x00000000:
266 				if (device->chipset == 0xa0) /* wtf?? */
269 			case 0x00000400:
270 				return 0;
271 			case 0x00000800:
272 				if (mast & 0x01000000)
273 					return read_pll(clk, 0x004028) >> P;
274 				return read_pll(clk, 0x004030) >> P;
275 			case 0x00000c00:
279 		case 0x98:
280 			switch (mast & 0x00000c00) {
281 			case 0x00000000:
283 			case 0x00000400:
284 				return 0;
285 			case 0x00000800:
287 			case 0x00000c00:
295 		case 0x50:
296 		case 0xa0:
297 			return read_pll(clk, 0x00e810) >> 2;
298 		case 0x84:
299 		case 0x86:
300 		case 0x92:
301 		case 0x94:
302 		case 0x96:
303 		case 0x98:
304 			P = (read_div(clk) & 0x00000007) >> 0;
305 			switch (mast & 0x0c000000) {
306 			case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
307 			case 0x04000000: break;
308 			case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);
309 			case 0x0c000000:
334 		return 0;
336 	pll.vco2.max_freq = 0;
339 		return 0;
348 	for (*div = 0; *div <= 7; (*div)++) {
350 			clk1 = clk0 << (*div ? 1 : 0);
379 	u32 mastm = 0, mastv = 0;
380 	u32 divsm = 0, divsv = 0;
389 	clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */
391 	clk_setf(hwsq, 0x10, 0x00); /* disable fb */
392 	clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
403 		if (device->chipset != 0x98)
404 			out = read_pll(clk, 0x004030);
411 			if (device->chipset != 0x98)
412 				mastv |= 0x00000c00;
415 			mastv |= 0x00000800;
419 		mastm |= 0x00000c00;
420 		divsm |= 0x00000700;
428 			mastv |= 0x00000000;
431 			mastv |= 0x08000000;
436 			mastv |= 0x0c000000;
440 		mastm |= 0x0c000000;
441 		divsm |= 0x00000007;
447 	clk_mask(hwsq, mast, mastm, 0x00000000);
454 	if (device->chipset < 0x92)
455 		clk_mask(hwsq, mast, 0x001000b0, 0x00100080);
457 		clk_mask(hwsq, mast, 0x000000b3, 0x00000081);
460 	freq = calc_pll(clk, 0x4028, core, &N, &M, &P1);
461 	if (freq == 0)
464 	clk_mask(hwsq, nvpll[0], 0xc03f0100,
465 				 0x80000000 | (P1 << 19) | (P1 << 16));
466 	clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);
475 		clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));
476 		clk_mask(hwsq, mast, 0x00100033, 0x00000023);
478 		freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1);
479 		if (freq == 0)
482 		clk_mask(hwsq, spll[0], 0xc03f0100,
483 					0x80000000 | (P1 << 19) | (P1 << 16));
484 		clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
485 		clk_mask(hwsq, mast, 0x00100033, 0x00000033);
489 	clk_setf(hwsq, 0x10, 0x01); /* enable fb */
490 	clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
491 	clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */
492 	return 0;
523 	clk->hwsq.r_fifo = hwsq_reg(0x002504);
524 	clk->hwsq.r_spll[0] = hwsq_reg(0x004020);
525 	clk->hwsq.r_spll[1] = hwsq_reg(0x004024);
526 	clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028);
527 	clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);
529 	case 0x92:
530 	case 0x94:
531 	case 0x96:
532 		clk->hwsq.r_divs = hwsq_reg(0x004800);
535 		clk->hwsq.r_divs = hwsq_reg(0x004700);
538 	clk->hwsq.r_mast = hwsq_reg(0x00c040);
539 	return 0;
549 		{ nv_clk_src_crystal, 0xff },
550 		{ nv_clk_src_href   , 0xff },
551 		{ nv_clk_src_core   , 0xff, 0, "core", 1000 },
552 		{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
553 		{ nv_clk_src_mem    , 0xff, 0, "memory", 1000 },