subdev/clk/nv40.c

43 	u32 ctrl = nvkm_rd32(device, reg + 0x00);
44 	int P = (ctrl & 0x00070000) >> 16;
45 	int N = (ctrl & 0x0000ff00) >> 8;
46 	int M = (ctrl & 0x000000ff) >> 0;
47 	u32 ref = 27000, khz = 0;
49 	if (ctrl & 0x80000000)
59 	u32 ctrl = nvkm_rd32(device, reg + 0x00);
60 	u32 coef = nvkm_rd32(device, reg + 0x04);
61 	int N2 = (coef & 0xff000000) >> 24;
62 	int M2 = (coef & 0x00ff0000) >> 16;
63 	int N1 = (coef & 0x0000ff00) >> 8;
64 	int M1 = (coef & 0x000000ff) >> 0;
65 	int P = (ctrl & 0x00070000) >> 16;
66 	u32 ref = 27000, khz = 0;
68 	if ((ctrl & 0x80000000) && M1) {
70 		if ((ctrl & 0x40000100) == 0x40000000) {
74 				khz = 0;
86 		return read_pll_2(clk, 0x004000);
88 		return read_pll_1(clk, 0x004008);
93 	return 0;
102 	u32 mast = nvkm_rd32(device, 0x00c040);
110 		return read_clk(clk, (mast & 0x00000003) >> 0);
112 		return read_clk(clk, (mast & 0x00000030) >> 4);
114 		return read_pll_2(clk, 0x4020);
136 		pll.vco2.max_freq = 0;
139 	if (ret == 0)
155 	ret = nv40_clk_calc_pll(clk, 0x004000, gclk,
157 	if (ret < 0)
161 		clk->npll_ctrl = 0x80000100 | (log2P << 16);
164 		clk->npll_ctrl = 0xc0000000 | (log2P << 16);
170 		ret = nv40_clk_calc_pll(clk, 0x004008, sclk,
172 		if (ret < 0)
175 		clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
176 		clk->ctrl = 0x00000223;
178 		clk->spll = 0x00000000;
179 		clk->ctrl = 0x00000333;
182 	return 0;
190 	nvkm_mask(device, 0x00c040, 0x00000333, 0x00000000);
191 	nvkm_wr32(device, 0x004004, clk->npll_coef);
192 	nvkm_mask(device, 0x004000, 0xc0070100, clk->npll_ctrl);
193 	nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll);
195 	nvkm_mask(device, 0x00c040, 0x00000333, clk->ctrl);
196 	return 0;
211 		{ nv_clk_src_crystal, 0xff },
212 		{ nv_clk_src_href   , 0xff },
213 		{ nv_clk_src_core   , 0xff, 0, "core", 1000 },
214 		{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
215 		{ nv_clk_src_mem    , 0xff, 0, "memory", 1000 },