subdev/clk/mcp77.c

45 	return nvkm_rd32(device, 0x004600);
52 	u32 ctrl = nvkm_rd32(device, base + 0);
55 	u32 post_div = 0;
56 	u32 clock = 0;
60 	case 0x4020:
61 		post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16);
63 	case 0x4028:
64 		post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16;
70 	N1 = (coef & 0x0000ff00) >> 8;
71 	M1 = (coef & 0x000000ff);
72 	if ((ctrl & 0x80000000) && M1) {
86 	u32 mast = nvkm_rd32(device, 0x00c054);
87 	u32 P = 0;
99 		switch (mast & 0x000c0000) {
100 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3);
101 		case 0x00040000: break;
102 		case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4);
103 		case 0x000c0000: return nvkm_clk_read(&clk->base, nv_clk_src_cclk);
107 		P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16;
109 		switch (mast & 0x00000003) {
110 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
111 		case 0x00000001: return 0;
112 		case 0x00000002: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4) >> P;
113 		case 0x00000003: return read_pll(clk, 0x004028) >> P;
117 		if ((mast & 0x03000000) != 0x03000000)
120 		if ((mast & 0x00000200) == 0x00000000)
123 		switch (mast & 0x00000c00) {
124 		case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
125 		case 0x00000400: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4);
126 		case 0x00000800: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3);
127 		default: return 0;
130 		P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16;
131 		switch (mast & 0x00000030) {
132 		case 0x00000000:
133 			if (mast & 0x00000040)
136 		case 0x00000010: break;
137 		case 0x00000020: return read_pll(clk, 0x004028) >> P;
138 		case 0x00000030: return read_pll(clk, 0x004020) >> P;
142 		return 0;
144 		P = (read_div(clk) & 0x00000700) >> 8;
146 		switch (mast & 0x00400000) {
147 		case 0x00400000:
158 	return 0;
171 		return 0;
173 	pll.vco2.max_freq = 0;
176 		return 0;
185 	for (*div = 0; *div <= 7; (*div)++) {
187 			clk1 = clk0 << (*div ? 1 : 0);
207 	u32 out = 0, clock = 0;
208 	int N, M, P1, P2 = 0;
209 	int divs = 0;
216 	clock = calc_pll(clk, 0x4028, (core << 1), &N, &M, &P1);
238 	out = 0;
242 		clock = calc_pll(clk, 0x4020, shader, &N, &M, &P1);
292 	return 0;
301 	u32 pllmask = 0, mast;
304 	int ret = 0;
311 	mast = nvkm_mask(device, 0xc054, 0x03400e70, 0x03400640);
312 	mast &= ~0x00400e73;
313 	mast |= 0x03000000;
317 		nvkm_mask(device, 0x4028, 0x00070000, clk->cctrl);
318 		mast |= 0x00000002;
321 		nvkm_wr32(device, 0x402c, clk->ccoef);
322 		nvkm_wr32(device, 0x4028, 0x80000000 | clk->cctrl);
323 		nvkm_wr32(device, 0x4040, clk->cpost);
324 		pllmask |= (0x3 << 8);
325 		mast |= 0x00000003;
334 		nvkm_mask(device, 0x4020, 0x00070000, 0x00000000);
335 		/* mast |= 0x00000000; */
338 		nvkm_mask(device, 0x4020, 0x00070000, clk->sctrl);
339 		mast |= 0x00000020;
342 		nvkm_wr32(device, 0x4024, clk->scoef);
343 		nvkm_wr32(device, 0x4020, 0x80000000 | clk->sctrl);
344 		nvkm_wr32(device, 0x4070, clk->spost);
345 		pllmask |= (0x3 << 12);
346 		mast |= 0x00000030;
354 		u32 tmp = nvkm_rd32(device, 0x004080) & pllmask;
357 	) < 0)
362 		mast |= 0x00400000;
365 		nvkm_wr32(device, 0x4600, clk->vdiv);
368 	nvkm_wr32(device, 0xc054, mast);
373 		nvkm_wr32(device, 0x4040, 0x00000000);
374 		nvkm_mask(device, 0x4028, 0x80000000, 0x00000000);
378 		nvkm_wr32(device, 0x4070, 0x00000000);
379 		nvkm_mask(device, 0x4020, 0x80000000, 0x00000000);
402 		{ nv_clk_src_crystal, 0xff },
403 		{ nv_clk_src_href   , 0xff },
404 		{ nv_clk_src_core   , 0xff, 0, "core", 1000 },
405 		{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
406 		{ nv_clk_src_vdec   , 0xff, 0, "vdec", 1000 },