Lines Matching defs:i
40 #define NV10_PFB_TILE(i) (0x00100240 + (i*16))
42 #define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))
43 #define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))
44 #define NV10_PFB_TSTATUS(i) (0x0010024c + (i*16))
49 #define NV20_PFB_ZCOMP(i) (0x00100300 + 4*(i))
55 #define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i))
56 #define NV40_PFB_TILE(i) (0x00100600 + (i*16))
59 #define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
60 #define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
61 #define NV40_PFB_TSTATUS(i) (0x0010060c + (i*16))
89 #define NV03_USER(i) (0x00800000+(i*NV03_USER_SIZE))
93 #define NV03_USER_DMA_PUT(i) (0x00800040+(i*NV03_USER_SIZE))
96 #define NV03_USER_DMA_GET(i) (0x00800044+(i*NV03_USER_SIZE))
99 #define NV03_USER_REF_CNT(i) (0x00800048+(i*NV03_USER_SIZE))
103 #define NV40_USER(i) (0x00c00000+(i*NV40_USER_SIZE))
105 #define NV40_USER_DMA_PUT(i) (0x00c00040+(i*NV40_USER_SIZE))
107 #define NV40_USER_DMA_GET(i) (0x00c00044+(i*NV40_USER_SIZE))
109 #define NV40_USER_REF_CNT(i) (0x00c00048+(i*NV40_USER_SIZE))
112 #define NV50_USER(i) (0x00c00000+(i*NV50_USER_SIZE))
114 #define NV50_USER_DMA_PUT(i) (0x00c00040+(i*NV50_USER_SIZE))
116 #define NV50_USER_DMA_GET(i) (0x00c00044+(i*NV50_USER_SIZE))
118 #define NV50_USER_REF_CNT(i) (0x00c00048+(i*NV50_USER_SIZE))
218 #define NV10_PGRAPH_CTX_SWITCH(i) (0x0040014C + 0x4*(i))
220 #define NV10_PGRAPH_CTX_CACHE(i, j) (0x00400160 \
221 + 0x4*(i) + 0x20*(j))
373 #define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16))
374 #define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16))
375 #define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16))
376 #define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16))
377 #define NV20_PGRAPH_ZCOMP(i) (0x00400980 + 4*(i))
378 #define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16))
379 #define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16))
380 #define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16))
381 #define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16))
383 #define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16))
384 #define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16))
385 #define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16))
386 #define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16))
434 #define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16))
435 #define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16))
436 #define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16))
437 #define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16))
565 #define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))
566 #define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))
567 #define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))
568 #define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))
643 #define NV50_AUXCH_DATA_OUT(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0)
645 #define NV50_AUXCH_DATA_IN(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0)
647 #define NV50_AUXCH_ADDR(i) ((i) * 0x50 + 0x0000e4e0)
648 #define NV50_AUXCH_CTRL(i) ((i) * 0x50 + 0x0000e4e4)
662 #define NV50_AUXCH_STAT(i) ((i) * 0x50 + 0x0000e4e8)
727 #define NV50_PDISPLAY_TRAPPED_ADDR(i) ((i) * 0x08 + 0x00610080)
728 #define NV50_PDISPLAY_TRAPPED_DATA(i) ((i) * 0x08 + 0x00610084)
729 #define NV50_PDISPLAY_EVO_CTRL(i) ((i) * 0x10 + 0x00610200)
733 #define NV50_PDISPLAY_EVO_DMA_CB(i) ((i) * 0x10 + 0x00610204)
738 #define NV50_PDISPLAY_EVO_UNK2(i) ((i) * 0x10 + 0x00610208)
739 #define NV50_PDISPLAY_EVO_HASH_TAG(i) ((i) * 0x10 + 0x0061020c)
742 #define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i) ((i) * 0x10 + 0x00610270)
753 #define NV50_PDISPLAY_CRTC_P(i, r) ((i) * 0x540 + NV50_PDISPLAY_CRTC_##r)
754 #define NV50_PDISPLAY_CRTC_C(i, r) (4 + (i) * 0x540 + NV50_PDISPLAY_CRTC_##r)
780 #define NV50_PDISPLAY_DAC_MODE_CTRL_P(i) (0x00610b58 + (i) * 0x8)
781 #define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8)
782 #define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610b70 + (i) * 0x8)
783 #define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610b74 + (i) * 0x8)
784 #define NV50_PDISPLAY_EXT_MODE_CTRL_P(i) (0x00610b80 + (i) * 0x8)
785 #define NV50_PDISPLAY_EXT_MODE_CTRL_C(i) (0x00610b84 + (i) * 0x8)
786 #define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610bdc + (i) * 0x8)
787 #define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610be0 + (i) * 0x8)
788 #define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610794 + (i) * 0x8)
789 #define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610798 + (i) * 0x8)
792 #define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100)
794 #define NV50_PDISPLAY_CRTC_CLK_VPLL_A(i) ((i) * 0x800 + 0x614104)
795 #define NV50_PDISPLAY_CRTC_CLK_VPLL_B(i) ((i) * 0x800 + 0x614108)
796 #define NV50_PDISPLAY_CRTC_CLK_CTRL2(i) ((i) * 0x800 + 0x614200)
799 #define NV50_PDISPLAY_DAC_CLK_CTRL2(i) ((i) * 0x800 + 0x614280)
802 #define NV50_PDISPLAY_SOR_CLK_CTRL2(i) ((i) * 0x800 + 0x614300)
807 #define NV50_PDISPLAY_DAC_DPMS_CTRL(i) (0x0061a004 + (i) * 0x800)
813 #define NV50_PDISPLAY_DAC_LOAD_CTRL(i) (0x0061a00c + (i) * 0x800)
817 #define NV50_PDISPLAY_DAC_CLK_CTRL1(i) (0x0061a010 + (i) * 0x800)
821 #define NV50_PDISPLAY_SOR_DPMS_CTRL(i) (0x0061c004 + (i) * 0x800)
824 #define NV50_PDISPLAY_SOR_CLK_CTRL1(i) (0x0061c008 + (i) * 0x800)
826 #define NV50_PDISPLAY_SOR_DPMS_STATE(i) (0x0061c030 + (i) * 0x800)
830 #define NV50_PDISP_SOR_PWM_DIV(i) (0x0061c080 + (i) * 0x800)
831 #define NV50_PDISP_SOR_PWM_CTL(i) (0x0061c084 + (i) * 0x800)
836 #define NV50_SOR_DP_CTRL(i, l) (0x0061c10c + (i) * 0x800 + (l) * 0x80)
848 #define NV50_SOR_DP_UNK118(i, l) (0x0061c118 + (i) * 0x800 + (l) * 0x80)
849 #define NV50_SOR_DP_UNK120(i, l) (0x0061c120 + (i) * 0x800 + (l) * 0x80)
850 #define NV50_SOR_DP_SCFG(i, l) (0x0061c128 + (i) * 0x800 + (l) * 0x80)
851 #define NV50_SOR_DP_UNK130(i, l) (0x0061c130 + (i) * 0x800 + (l) * 0x80)
853 #define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000)
854 #define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000)
855 #define NV50_PDISPLAY_USER_GET(i) ((i) * 0x1000 + 0x00640004)
858 #define NV50_PDISPLAY_CURSOR_USER_POS_CTRL(i) ((i) * 0x1000 + 0x00647080)
859 #define NV50_PDISPLAY_CURSOR_USER_POS(i) ((i) * 0x1000 + 0x00647084)