nouveau/dispnv04/hw.h

37 void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);
38 uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index);
39 void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value);
40 uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index);
42 void NVBlankScreen(struct drm_device *, int head, bool blank);
48 void nouveau_hw_save_state(struct drm_device *, int head,
50 void nouveau_hw_load_state(struct drm_device *, int head,
52 void nouveau_hw_load_state_palette(struct drm_device *, int head,
60 					int head, uint32_t reg)
64 	if (head)
71 					int head, uint32_t reg, uint32_t val)
74 	if (head)
80 					int head, uint32_t reg)
84 	if (head)
91 					int head, uint32_t reg, uint32_t val)
94 	if (head)
120 					int head, uint8_t index, uint8_t value)
123 	nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
124 	nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
128 					int head, uint8_t index)
132 	nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
133 	val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
139  * per-head variables around
152 NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value)
154 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
155 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value);
158 static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index)
160 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
161 	return NVReadVgaCrtc(dev, head, NV_CIO_CRE_58);
165 					int head, uint32_t reg)
172 	 * NVSetOwner for the relevant head to be programmed */
173 	if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
181 					int head, uint32_t reg, uint8_t value)
187 	 * NVSetOwner for the relevant head to be programmed */
188 	if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
194 static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
197 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
198 	nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
201 static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
204 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
205 	return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
209 					int head, uint8_t index, uint8_t value)
212 	if (NVGetEnablePalette(dev, head))
217 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
218 	nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
219 	nvif_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
223 					int head, uint8_t index)
227 	if (NVGetEnablePalette(dev, head))
232 	nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
233 	nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
234 	val = nvif_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
238 static inline void NVVgaSeqReset(struct drm_device *dev, int head, bool start)
240 	NVWriteVgaSeq(dev, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);
243 static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
245 	uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
248 		NVVgaSeqReset(dev, head, true);
249 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
252 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);   /* reenable display */
253 		NVVgaSeqReset(dev, head, false);
255 	NVSetEnablePalette(dev, head, protect);
270 /* makes cr0-7 on the specified head read-only */
272 nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock)
274 	uint8_t cr11 = NVReadVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX);
281 	NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11);
287 nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock)
303 		cr21 = NVReadVgaCrtc(dev, head, NV_CIO_CRE_21) | 0xfa;
305 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21);
341 nv_fix_nv40_hw_cursor(struct drm_device *dev, int head)
348 	uint32_t curpos = NVReadRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS);
349 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS, curpos);
353 nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
357 	NVWriteCRTC(dev, head, NV_PCRTC_START, offset);
364 		int cre_heb = NVReadVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX);
366 		NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX,
372 nv_show_cursor(struct drm_device *dev, int head, bool show)
376 		&nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
382 	NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
385 		nv_fix_nv40_hw_cursor(dev, head);