Lines Matching defs:regp
397 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
401 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
403 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals);
408 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
410 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
413 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
415 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
417 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
418 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
419 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
420 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
421 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
422 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
423 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
424 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
428 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
429 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
433 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
435 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
436 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
440 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
441 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
445 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
448 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
449 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
451 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
454 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
457 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
458 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
459 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
462 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
473 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
478 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
480 clk->pll_prog(clk, pllreg, ®p->pllvals);
485 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
487 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
490 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
492 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
501 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
506 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
507 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
511 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
513 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
523 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
526 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
529 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
531 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
535 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
543 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
546 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
549 rd_cio_state(dev, head, regp, i);
553 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
557 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
560 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
567 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
570 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
573 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
577 wr_cio_state(dev, head, regp, i);
581 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
585 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
594 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
597 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
601 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
603 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
605 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
606 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
610 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
613 rd_cio_state(dev, head, regp, 0x9f);
615 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
618 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
619 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
622 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
623 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
626 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
629 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
632 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
633 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
636 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
638 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
639 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
641 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
642 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
644 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
648 rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
649 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
650 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
653 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
654 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
655 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
657 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
658 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
661 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
670 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
680 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
692 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
693 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
694 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
697 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
700 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
703 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)
710 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
712 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
720 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
723 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
726 wr_cio_state(dev, head, regp, 0x9f);
728 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
731 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
734 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
736 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
737 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
739 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
742 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
759 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
761 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
764 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
765 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
766 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
768 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
769 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
772 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);