Lines Matching full:gpu
25 static int enable_pwrrail(struct msm_gpu *gpu) in enable_pwrrail() argument
27 struct drm_device *dev = gpu->dev; in enable_pwrrail()
30 if (gpu->gpu_reg) { in enable_pwrrail()
31 ret = regulator_enable(gpu->gpu_reg); in enable_pwrrail()
38 if (gpu->gpu_cx) { in enable_pwrrail()
39 ret = regulator_enable(gpu->gpu_cx); in enable_pwrrail()
49 static int disable_pwrrail(struct msm_gpu *gpu) in disable_pwrrail() argument
51 if (gpu->gpu_cx) in disable_pwrrail()
52 regulator_disable(gpu->gpu_cx); in disable_pwrrail()
53 if (gpu->gpu_reg) in disable_pwrrail()
54 regulator_disable(gpu->gpu_reg); in disable_pwrrail()
58 static int enable_clk(struct msm_gpu *gpu) in enable_clk() argument
60 if (gpu->core_clk && gpu->fast_rate) in enable_clk()
61 dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); in enable_clk()
64 if (gpu->rbbmtimer_clk) in enable_clk()
65 clk_set_rate(gpu->rbbmtimer_clk, 19200000); in enable_clk()
67 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); in enable_clk()
70 static int disable_clk(struct msm_gpu *gpu) in disable_clk() argument
72 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); in disable_clk()
79 if (gpu->core_clk) in disable_clk()
80 dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); in disable_clk()
82 if (gpu->rbbmtimer_clk) in disable_clk()
83 clk_set_rate(gpu->rbbmtimer_clk, 0); in disable_clk()
88 static int enable_axi(struct msm_gpu *gpu) in enable_axi() argument
90 return clk_prepare_enable(gpu->ebi1_clk); in enable_axi()
93 static int disable_axi(struct msm_gpu *gpu) in disable_axi() argument
95 clk_disable_unprepare(gpu->ebi1_clk); in disable_axi()
99 int msm_gpu_pm_resume(struct msm_gpu *gpu) in msm_gpu_pm_resume() argument
103 DBG("%s", gpu->name); in msm_gpu_pm_resume()
106 ret = enable_pwrrail(gpu); in msm_gpu_pm_resume()
110 ret = enable_clk(gpu); in msm_gpu_pm_resume()
114 ret = enable_axi(gpu); in msm_gpu_pm_resume()
118 msm_devfreq_resume(gpu); in msm_gpu_pm_resume()
120 gpu->needs_hw_init = true; in msm_gpu_pm_resume()
125 int msm_gpu_pm_suspend(struct msm_gpu *gpu) in msm_gpu_pm_suspend() argument
129 DBG("%s", gpu->name); in msm_gpu_pm_suspend()
132 msm_devfreq_suspend(gpu); in msm_gpu_pm_suspend()
134 ret = disable_axi(gpu); in msm_gpu_pm_suspend()
138 ret = disable_clk(gpu); in msm_gpu_pm_suspend()
142 ret = disable_pwrrail(gpu); in msm_gpu_pm_suspend()
146 gpu->suspend_count++; in msm_gpu_pm_suspend()
151 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_context *ctx, in msm_gpu_show_fdinfo() argument
154 drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns); in msm_gpu_show_fdinfo()
155 drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles); in msm_gpu_show_fdinfo()
156 drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate); in msm_gpu_show_fdinfo()
159 int msm_gpu_hw_init(struct msm_gpu *gpu) in msm_gpu_hw_init() argument
163 WARN_ON(!mutex_is_locked(&gpu->lock)); in msm_gpu_hw_init()
165 if (!gpu->needs_hw_init) in msm_gpu_hw_init()
168 disable_irq(gpu->irq); in msm_gpu_hw_init()
169 ret = gpu->funcs->hw_init(gpu); in msm_gpu_hw_init()
171 gpu->needs_hw_init = false; in msm_gpu_hw_init()
172 enable_irq(gpu->irq); in msm_gpu_hw_init()
181 struct msm_gpu *gpu = data; in msm_gpu_devcoredump_read() local
186 state = msm_gpu_crashstate_get(gpu); in msm_gpu_devcoredump_read()
206 gpu->funcs->show(gpu, state, &p); in msm_gpu_devcoredump_read()
208 msm_gpu_crashstate_put(gpu); in msm_gpu_devcoredump_read()
215 struct msm_gpu *gpu = data; in msm_gpu_devcoredump_free() local
217 msm_gpu_crashstate_put(gpu); in msm_gpu_devcoredump_free()
363 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, in msm_gpu_crashstate_capture() argument
370 if (!gpu->funcs->gpu_state_get) in msm_gpu_crashstate_capture()
374 if (gpu->crashstate) in msm_gpu_crashstate_capture()
377 state = gpu->funcs->gpu_state_get(gpu); in msm_gpu_crashstate_capture()
402 gpu->crashstate = state; in msm_gpu_crashstate_capture()
404 dev_coredumpm(&gpu->pdev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, in msm_gpu_crashstate_capture()
408 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, in msm_gpu_crashstate_capture() argument
416 * Hangcheck detection for locked gpu:
437 static void retire_submits(struct msm_gpu *gpu);
444 WARN_ON(!mutex_is_locked(&submit->gpu->lock)); in get_comm_cmdline()
465 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); in recover_worker() local
466 struct drm_device *dev = gpu->dev; in recover_worker()
469 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); in recover_worker()
474 mutex_lock(&gpu->lock); in recover_worker()
476 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name); in recover_worker()
482 * or waiting to acquire the gpu lock, then nothing more to do. in recover_worker()
492 gpu->global_faults++; in recover_worker()
512 gpu->name, comm, cmd); in recover_worker()
517 DRM_DEV_ERROR(dev->dev, "%s: offending task: unknown\n", gpu->name); in recover_worker()
523 pm_runtime_get_sync(&gpu->pdev->dev); in recover_worker()
524 msm_gpu_crashstate_capture(gpu, submit, NULL, comm, cmd); in recover_worker()
534 for (i = 0; i < gpu->nr_rings; i++) { in recover_worker()
535 struct msm_ringbuffer *ring = gpu->rb[i]; in recover_worker()
549 if (msm_gpu_active(gpu)) { in recover_worker()
551 retire_submits(gpu); in recover_worker()
553 gpu->funcs->recover(gpu); in recover_worker()
559 for (i = 0; i < gpu->nr_rings; i++) { in recover_worker()
560 struct msm_ringbuffer *ring = gpu->rb[i]; in recover_worker()
571 gpu->funcs->submit(gpu, submit); in recover_worker()
577 pm_runtime_put(&gpu->pdev->dev); in recover_worker()
580 mutex_unlock(&gpu->lock); in recover_worker()
582 msm_gpu_retire(gpu); in recover_worker()
585 void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info) in msm_gpu_fault_crashstate_capture() argument
588 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); in msm_gpu_fault_crashstate_capture()
591 mutex_lock(&gpu->lock); in msm_gpu_fault_crashstate_capture()
601 * When we get GPU iova faults, we can get 1000s of them, in msm_gpu_fault_crashstate_capture()
608 pm_runtime_get_sync(&gpu->pdev->dev); in msm_gpu_fault_crashstate_capture()
609 msm_gpu_crashstate_capture(gpu, submit, fault_info, comm, cmd); in msm_gpu_fault_crashstate_capture()
610 pm_runtime_put_sync(&gpu->pdev->dev); in msm_gpu_fault_crashstate_capture()
616 mutex_unlock(&gpu->lock); in msm_gpu_fault_crashstate_capture()
619 static void hangcheck_timer_reset(struct msm_gpu *gpu) in hangcheck_timer_reset() argument
621 struct msm_drm_private *priv = gpu->dev->dev_private; in hangcheck_timer_reset()
622 mod_timer(&gpu->hangcheck_timer, in hangcheck_timer_reset()
626 static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in made_progress() argument
631 if (!gpu->funcs->progress) in made_progress()
634 if (!gpu->funcs->progress(gpu, ring)) in made_progress()
643 struct msm_gpu *gpu = timer_container_of(gpu, t, hangcheck_timer); in hangcheck_handler() local
644 struct drm_device *dev = gpu->dev; in hangcheck_handler()
645 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in hangcheck_handler()
653 !made_progress(gpu, ring)) { in hangcheck_handler()
657 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", in hangcheck_handler()
658 gpu->name, ring->id); in hangcheck_handler()
660 gpu->name, fence); in hangcheck_handler()
662 gpu->name, ring->fctx->last_fence); in hangcheck_handler()
664 kthread_queue_work(gpu->worker, &gpu->recover_work); in hangcheck_handler()
669 hangcheck_timer_reset(gpu); in hangcheck_handler()
672 msm_gpu_retire(gpu); in hangcheck_handler()
680 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) in update_hw_cntrs() argument
682 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; in update_hw_cntrs()
683 int i, n = min(ncntrs, gpu->num_perfcntrs); in update_hw_cntrs()
686 for (i = 0; i < gpu->num_perfcntrs; i++) in update_hw_cntrs()
687 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); in update_hw_cntrs()
691 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; in update_hw_cntrs()
694 for (i = 0; i < gpu->num_perfcntrs; i++) in update_hw_cntrs()
695 gpu->last_cntrs[i] = current_cntrs[i]; in update_hw_cntrs()
700 static void update_sw_cntrs(struct msm_gpu *gpu) in update_sw_cntrs() argument
706 spin_lock_irqsave(&gpu->perf_lock, flags); in update_sw_cntrs()
707 if (!gpu->perfcntr_active) in update_sw_cntrs()
711 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); in update_sw_cntrs()
713 gpu->totaltime += elapsed; in update_sw_cntrs()
714 if (gpu->last_sample.active) in update_sw_cntrs()
715 gpu->activetime += elapsed; in update_sw_cntrs()
717 gpu->last_sample.active = msm_gpu_active(gpu); in update_sw_cntrs()
718 gpu->last_sample.time = time; in update_sw_cntrs()
721 spin_unlock_irqrestore(&gpu->perf_lock, flags); in update_sw_cntrs()
724 void msm_gpu_perfcntr_start(struct msm_gpu *gpu) in msm_gpu_perfcntr_start() argument
728 pm_runtime_get_sync(&gpu->pdev->dev); in msm_gpu_perfcntr_start()
730 spin_lock_irqsave(&gpu->perf_lock, flags); in msm_gpu_perfcntr_start()
732 gpu->last_sample.active = msm_gpu_active(gpu); in msm_gpu_perfcntr_start()
733 gpu->last_sample.time = ktime_get(); in msm_gpu_perfcntr_start()
734 gpu->activetime = gpu->totaltime = 0; in msm_gpu_perfcntr_start()
735 gpu->perfcntr_active = true; in msm_gpu_perfcntr_start()
736 update_hw_cntrs(gpu, 0, NULL); in msm_gpu_perfcntr_start()
737 spin_unlock_irqrestore(&gpu->perf_lock, flags); in msm_gpu_perfcntr_start()
740 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) in msm_gpu_perfcntr_stop() argument
742 gpu->perfcntr_active = false; in msm_gpu_perfcntr_stop()
743 pm_runtime_put_sync(&gpu->pdev->dev); in msm_gpu_perfcntr_stop()
747 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, in msm_gpu_perfcntr_sample() argument
753 spin_lock_irqsave(&gpu->perf_lock, flags); in msm_gpu_perfcntr_sample()
755 if (!gpu->perfcntr_active) { in msm_gpu_perfcntr_sample()
760 *activetime = gpu->activetime; in msm_gpu_perfcntr_sample()
761 *totaltime = gpu->totaltime; in msm_gpu_perfcntr_sample()
763 gpu->activetime = gpu->totaltime = 0; in msm_gpu_perfcntr_sample()
765 ret = update_hw_cntrs(gpu, ncntrs, cntrs); in msm_gpu_perfcntr_sample()
768 spin_unlock_irqrestore(&gpu->perf_lock, flags); in msm_gpu_perfcntr_sample()
777 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in retire_submit() argument
806 pm_runtime_mark_last_busy(&gpu->pdev->dev); in retire_submit()
813 mutex_lock(&gpu->active_lock); in retire_submit()
814 gpu->active_submits--; in retire_submit()
815 WARN_ON(gpu->active_submits < 0); in retire_submit()
816 if (!gpu->active_submits) { in retire_submit()
817 msm_devfreq_idle(gpu); in retire_submit()
818 pm_runtime_put_autosuspend(&gpu->pdev->dev); in retire_submit()
821 mutex_unlock(&gpu->active_lock); in retire_submit()
826 static void retire_submits(struct msm_gpu *gpu) in retire_submits() argument
831 for (i = 0; i < gpu->nr_rings; i++) { in retire_submits()
832 struct msm_ringbuffer *ring = gpu->rb[i]; in retire_submits()
849 retire_submit(gpu, ring, submit); in retire_submits()
856 wake_up_all(&gpu->retire_event); in retire_submits()
861 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); in retire_worker() local
863 retire_submits(gpu); in retire_worker()
867 void msm_gpu_retire(struct msm_gpu *gpu) in msm_gpu_retire() argument
871 for (i = 0; i < gpu->nr_rings; i++) in msm_gpu_retire()
872 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence); in msm_gpu_retire()
874 kthread_queue_work(gpu->worker, &gpu->retire_work); in msm_gpu_retire()
875 update_sw_cntrs(gpu); in msm_gpu_retire()
878 /* add bo's to gpu's ring, and kick gpu: */
879 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in msm_gpu_submit() argument
884 WARN_ON(!mutex_is_locked(&gpu->lock)); in msm_gpu_submit()
886 pm_runtime_get_sync(&gpu->pdev->dev); in msm_gpu_submit()
888 msm_gpu_hw_init(gpu); in msm_gpu_submit()
892 update_sw_cntrs(gpu); in msm_gpu_submit()
905 mutex_lock(&gpu->active_lock); in msm_gpu_submit()
906 if (!gpu->active_submits) { in msm_gpu_submit()
907 pm_runtime_get(&gpu->pdev->dev); in msm_gpu_submit()
908 msm_devfreq_active(gpu); in msm_gpu_submit()
910 gpu->active_submits++; in msm_gpu_submit()
911 mutex_unlock(&gpu->active_lock); in msm_gpu_submit()
913 gpu->funcs->submit(gpu, submit); in msm_gpu_submit()
916 pm_runtime_put(&gpu->pdev->dev); in msm_gpu_submit()
917 hangcheck_timer_reset(gpu); in msm_gpu_submit()
926 struct msm_gpu *gpu = data; in irq_handler() local
927 return gpu->funcs->irq(gpu); in irq_handler()
930 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) in get_clocks() argument
932 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks); in get_clocks()
935 gpu->nr_clocks = 0; in get_clocks()
939 gpu->nr_clocks = ret; in get_clocks()
941 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, in get_clocks()
942 gpu->nr_clocks, "core"); in get_clocks()
944 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, in get_clocks()
945 gpu->nr_clocks, "rbbmtimer"); in get_clocks()
952 msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task, in msm_gpu_create_private_vm() argument
957 if (!gpu) in msm_gpu_create_private_vm()
964 if (gpu->funcs->create_private_vm) { in msm_gpu_create_private_vm()
965 vm = gpu->funcs->create_private_vm(gpu, kernel_managed); in msm_gpu_create_private_vm()
971 vm = drm_gpuvm_get(gpu->vm); in msm_gpu_create_private_vm()
977 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, in msm_gpu_init() argument
985 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) in msm_gpu_init()
986 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); in msm_gpu_init()
988 gpu->dev = drm; in msm_gpu_init()
989 gpu->funcs = funcs; in msm_gpu_init()
990 gpu->name = name; in msm_gpu_init()
992 gpu->worker = kthread_run_worker(0, "gpu-worker"); in msm_gpu_init()
993 if (IS_ERR(gpu->worker)) { in msm_gpu_init()
994 ret = PTR_ERR(gpu->worker); in msm_gpu_init()
995 gpu->worker = NULL; in msm_gpu_init()
999 sched_set_fifo_low(gpu->worker->task); in msm_gpu_init()
1001 mutex_init(&gpu->active_lock); in msm_gpu_init()
1002 mutex_init(&gpu->lock); in msm_gpu_init()
1003 init_waitqueue_head(&gpu->retire_event); in msm_gpu_init()
1004 kthread_init_work(&gpu->retire_work, retire_worker); in msm_gpu_init()
1005 kthread_init_work(&gpu->recover_work, recover_worker); in msm_gpu_init()
1017 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); in msm_gpu_init()
1019 spin_lock_init(&gpu->perf_lock); in msm_gpu_init()
1023 gpu->mmio = msm_ioremap(pdev, config->ioname); in msm_gpu_init()
1024 if (IS_ERR(gpu->mmio)) { in msm_gpu_init()
1025 ret = PTR_ERR(gpu->mmio); in msm_gpu_init()
1030 gpu->irq = platform_get_irq(pdev, 0); in msm_gpu_init()
1031 if (gpu->irq < 0) { in msm_gpu_init()
1032 ret = gpu->irq; in msm_gpu_init()
1036 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, in msm_gpu_init()
1037 IRQF_TRIGGER_HIGH, "gpu-irq", gpu); in msm_gpu_init()
1039 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); in msm_gpu_init()
1043 ret = get_clocks(pdev, gpu); in msm_gpu_init()
1047 gpu->ebi1_clk = msm_clk_get(pdev, "bus"); in msm_gpu_init()
1048 DBG("ebi1_clk: %p", gpu->ebi1_clk); in msm_gpu_init()
1049 if (IS_ERR(gpu->ebi1_clk)) in msm_gpu_init()
1050 gpu->ebi1_clk = NULL; in msm_gpu_init()
1053 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); in msm_gpu_init()
1054 DBG("gpu_reg: %p", gpu->gpu_reg); in msm_gpu_init()
1055 if (IS_ERR(gpu->gpu_reg)) in msm_gpu_init()
1056 gpu->gpu_reg = NULL; in msm_gpu_init()
1058 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); in msm_gpu_init()
1059 DBG("gpu_cx: %p", gpu->gpu_cx); in msm_gpu_init()
1060 if (IS_ERR(gpu->gpu_cx)) in msm_gpu_init()
1061 gpu->gpu_cx = NULL; in msm_gpu_init()
1063 platform_set_drvdata(pdev, &gpu->adreno_smmu); in msm_gpu_init()
1065 msm_devfreq_init(gpu); in msm_gpu_init()
1067 gpu->vm = gpu->funcs->create_vm(gpu, pdev); in msm_gpu_init()
1068 if (IS_ERR(gpu->vm)) { in msm_gpu_init()
1069 ret = PTR_ERR(gpu->vm); in msm_gpu_init()
1075 check_apriv(gpu, MSM_BO_WC), gpu->vm, &gpu->memptrs_bo, in msm_gpu_init()
1084 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs"); in msm_gpu_init()
1086 if (nr_rings > ARRAY_SIZE(gpu->rb)) { in msm_gpu_init()
1088 ARRAY_SIZE(gpu->rb)); in msm_gpu_init()
1089 nr_rings = ARRAY_SIZE(gpu->rb); in msm_gpu_init()
1094 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); in msm_gpu_init()
1096 if (IS_ERR(gpu->rb[i])) { in msm_gpu_init()
1097 ret = PTR_ERR(gpu->rb[i]); in msm_gpu_init()
1107 gpu->nr_rings = nr_rings; in msm_gpu_init()
1109 refcount_set(&gpu->sysprof_active, 1); in msm_gpu_init()
1114 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { in msm_gpu_init()
1115 msm_ringbuffer_destroy(gpu->rb[i]); in msm_gpu_init()
1116 gpu->rb[i] = NULL; in msm_gpu_init()
1119 msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm); in msm_gpu_init()
1125 void msm_gpu_cleanup(struct msm_gpu *gpu) in msm_gpu_cleanup() argument
1129 DBG("%s", gpu->name); in msm_gpu_cleanup()
1131 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { in msm_gpu_cleanup()
1132 msm_ringbuffer_destroy(gpu->rb[i]); in msm_gpu_cleanup()
1133 gpu->rb[i] = NULL; in msm_gpu_cleanup()
1136 msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm); in msm_gpu_cleanup()
1138 if (!IS_ERR_OR_NULL(gpu->vm)) { in msm_gpu_cleanup()
1139 struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu; in msm_gpu_cleanup()
1141 drm_gpuvm_put(gpu->vm); in msm_gpu_cleanup()
1144 if (gpu->worker) { in msm_gpu_cleanup()
1145 kthread_destroy_worker(gpu->worker); in msm_gpu_cleanup()
1148 msm_devfreq_cleanup(gpu); in msm_gpu_cleanup()
1150 platform_set_drvdata(gpu->pdev, NULL); in msm_gpu_cleanup()