Lines Matching refs:ctrl
145 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) in msm_dp_read_ahb() argument
147 return readl_relaxed(ctrl->ahb_base + offset); in msm_dp_read_ahb()
150 static inline void msm_dp_write_ahb(struct msm_dp_ctrl_private *ctrl, in msm_dp_write_ahb() argument
157 writel(data, ctrl->ahb_base + offset); in msm_dp_write_ahb()
160 static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 offset) in msm_dp_read_link() argument
162 return readl_relaxed(ctrl->link_base + offset); in msm_dp_read_link()
165 static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, in msm_dp_write_link() argument
172 writel(data, ctrl->link_base + offset); in msm_dp_write_link()
207 struct msm_dp_ctrl_private *ctrl = in msm_dp_ctrl_reset() local
211 sw_reset = msm_dp_read_ahb(ctrl, REG_DP_SW_RESET); in msm_dp_ctrl_reset()
214 msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset); in msm_dp_ctrl_reset()
218 msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset); in msm_dp_ctrl_reset()
220 if (!ctrl->hw_revision) { in msm_dp_ctrl_reset()
221 ctrl->hw_revision = msm_dp_read_ahb(ctrl, REG_DP_HW_VERSION); in msm_dp_ctrl_reset()
222 ctrl->panel->hw_revision = ctrl->hw_revision; in msm_dp_ctrl_reset()
226 static u32 msm_dp_ctrl_get_aux_interrupt(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_get_aux_interrupt() argument
230 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS); in msm_dp_ctrl_get_aux_interrupt()
234 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, in msm_dp_ctrl_get_aux_interrupt()
241 static u32 msm_dp_ctrl_get_interrupt(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_get_interrupt() argument
245 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS2); in msm_dp_ctrl_get_interrupt()
249 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, in msm_dp_ctrl_get_interrupt()
257 struct msm_dp_ctrl_private *ctrl = in msm_dp_ctrl_enable_irq() local
260 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, in msm_dp_ctrl_enable_irq()
262 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, in msm_dp_ctrl_enable_irq()
268 struct msm_dp_ctrl_private *ctrl = in msm_dp_ctrl_disable_irq() local
271 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00); in msm_dp_ctrl_disable_irq()
272 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00); in msm_dp_ctrl_disable_irq()
275 static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_get_psr_interrupt() argument
279 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS4); in msm_dp_ctrl_get_psr_interrupt()
282 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS4, intr_ack); in msm_dp_ctrl_get_psr_interrupt()
287 static void msm_dp_ctrl_config_psr_interrupt(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_config_psr_interrupt() argument
289 msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); in msm_dp_ctrl_config_psr_interrupt()
292 static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_psr_mainlink_enable() argument
296 val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_psr_mainlink_enable()
298 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); in msm_dp_ctrl_psr_mainlink_enable()
301 static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_psr_mainlink_disable() argument
305 val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_psr_mainlink_disable()
307 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); in msm_dp_ctrl_psr_mainlink_disable()
310 static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_mainlink_enable() argument
314 drm_dbg_dp(ctrl->drm_dev, "enable\n"); in msm_dp_ctrl_mainlink_enable()
316 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_mainlink_enable()
320 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_enable()
323 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_enable()
326 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_enable()
330 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_enable()
333 static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_mainlink_disable() argument
337 drm_dbg_dp(ctrl->drm_dev, "disable\n"); in msm_dp_ctrl_mainlink_disable()
339 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_mainlink_disable()
341 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_disable()
344 static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) in msm_dp_setup_peripheral_flush() argument
348 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_setup_peripheral_flush()
350 if (ctrl->hw_revision >= DP_HW_VERSION_1_2) in msm_dp_setup_peripheral_flush()
355 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_setup_peripheral_flush()
358 static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_mainlink_ready() argument
364 ret = readl_poll_timeout(ctrl->link_base + REG_DP_MAINLINK_READY, in msm_dp_ctrl_mainlink_ready()
377 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_push_idle() local
379 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_push_idle()
381 reinit_completion(&ctrl->idle_comp); in msm_dp_ctrl_push_idle()
382 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); in msm_dp_ctrl_push_idle()
384 if (!wait_for_completion_timeout(&ctrl->idle_comp, in msm_dp_ctrl_push_idle()
388 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); in msm_dp_ctrl_push_idle()
391 static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_config_ctrl() argument
394 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_config_ctrl()
399 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) in msm_dp_ctrl_config_ctrl()
406 tbd = msm_dp_link_get_test_bits_depth(ctrl->link, in msm_dp_ctrl_config_ctrl()
407 ctrl->panel->msm_dp_mode.bpp); in msm_dp_ctrl_config_ctrl()
412 config |= ((ctrl->link->link_params.num_lanes - 1) in msm_dp_ctrl_config_ctrl()
424 if (ctrl->panel->psr_cap.version) in msm_dp_ctrl_config_ctrl()
427 drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=0x%x\n", config); in msm_dp_ctrl_config_ctrl()
429 msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); in msm_dp_ctrl_config_ctrl()
432 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_lane_mapping() argument
434 u32 *lane_map = ctrl->link->lane_map; in msm_dp_ctrl_lane_mapping()
442 msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, in msm_dp_ctrl_lane_mapping()
446 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_configure_source_params() argument
450 msm_dp_ctrl_lane_mapping(ctrl); in msm_dp_ctrl_configure_source_params()
451 msm_dp_setup_peripheral_flush(ctrl); in msm_dp_ctrl_configure_source_params()
453 msm_dp_ctrl_config_ctrl(ctrl); in msm_dp_ctrl_configure_source_params()
455 test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->panel->msm_dp_mode.bpp); in msm_dp_ctrl_configure_source_params()
456 colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link); in msm_dp_ctrl_configure_source_params()
458 misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); in msm_dp_ctrl_configure_source_params()
467 drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val); in msm_dp_ctrl_configure_source_params()
468 msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); in msm_dp_ctrl_configure_source_params()
470 msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); in msm_dp_ctrl_configure_source_params()
905 static void _dp_ctrl_calc_tu(struct msm_dp_ctrl_private *ctrl, in _dp_ctrl_calc_tu() argument
990 drm_dbg_dp(ctrl->drm_dev, in _dp_ctrl_calc_tu()
1026 drm_dbg_dp(ctrl->drm_dev, in _dp_ctrl_calc_tu()
1221 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n", in _dp_ctrl_calc_tu()
1223 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n", in _dp_ctrl_calc_tu()
1225 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n", in _dp_ctrl_calc_tu()
1227 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n", in _dp_ctrl_calc_tu()
1229 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n", in _dp_ctrl_calc_tu()
1231 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n", in _dp_ctrl_calc_tu()
1233 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n", in _dp_ctrl_calc_tu()
1239 static void msm_dp_ctrl_calc_tu_parameters(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_calc_tu_parameters() argument
1245 drm_mode = &ctrl->panel->msm_dp_mode.drm_mode; in msm_dp_ctrl_calc_tu_parameters()
1247 in.lclk = ctrl->link->link_params.rate / 1000; in msm_dp_ctrl_calc_tu_parameters()
1251 in.nlanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_calc_tu_parameters()
1252 in.bpp = ctrl->panel->msm_dp_mode.bpp; in msm_dp_ctrl_calc_tu_parameters()
1253 in.pixel_enc = ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; in msm_dp_ctrl_calc_tu_parameters()
1260 _dp_ctrl_calc_tu(ctrl, &in, tu_table); in msm_dp_ctrl_calc_tu_parameters()
1263 static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_setup_tr_unit() argument
1270 msm_dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); in msm_dp_ctrl_setup_tr_unit()
1286 msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary); in msm_dp_ctrl_setup_tr_unit()
1287 msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu); in msm_dp_ctrl_setup_tr_unit()
1288 msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2); in msm_dp_ctrl_setup_tr_unit()
1291 static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_wait4video_ready() argument
1295 if (!wait_for_completion_timeout(&ctrl->video_comp, in msm_dp_ctrl_wait4video_ready()
1303 static int msm_dp_ctrl_set_vx_px(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_set_vx_px() argument
1306 union phy_configure_opts *phy_opts = &ctrl->phy_opts; in msm_dp_ctrl_set_vx_px()
1312 phy_configure(ctrl->phy, phy_opts); in msm_dp_ctrl_set_vx_px()
1318 static int msm_dp_ctrl_update_phy_vx_px(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_update_phy_vx_px() argument
1321 struct msm_dp_link *link = ctrl->link; in msm_dp_ctrl_update_phy_vx_px()
1329 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_update_phy_vx_px()
1332 ret = msm_dp_ctrl_set_vx_px(ctrl, in msm_dp_ctrl_update_phy_vx_px()
1339 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_update_phy_vx_px()
1346 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_update_phy_vx_px()
1354 lane_cnt = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_update_phy_vx_px()
1359 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n", in msm_dp_ctrl_update_phy_vx_px()
1367 ret = drm_dp_dpcd_write(ctrl->aux, reg, buf, lane_cnt); in msm_dp_ctrl_update_phy_vx_px()
1374 static bool msm_dp_ctrl_train_pattern_set(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_train_pattern_set() argument
1381 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern); in msm_dp_ctrl_train_pattern_set()
1393 ret = drm_dp_dpcd_writeb(ctrl->aux, reg, buf); in msm_dp_ctrl_train_pattern_set()
1397 static int msm_dp_ctrl_set_pattern_state_bit(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_set_pattern_state_bit() argument
1404 drm_dbg_dp(ctrl->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit); in msm_dp_ctrl_set_pattern_state_bit()
1405 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit); in msm_dp_ctrl_set_pattern_state_bit()
1410 ret = readx_poll_timeout(readl, ctrl->link_base + REG_DP_MAINLINK_READY, in msm_dp_ctrl_set_pattern_state_bit()
1421 static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_link_train_1() argument
1429 delay_us = drm_dp_read_clock_recovery_delay(ctrl->aux, in msm_dp_ctrl_link_train_1()
1430 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_1()
1432 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_link_train_1()
1436 ret = msm_dp_ctrl_set_pattern_state_bit(ctrl, 1); in msm_dp_ctrl_link_train_1()
1439 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | in msm_dp_ctrl_link_train_1()
1442 msm_dp_link_reset_phy_params_vx_px(ctrl->link); in msm_dp_ctrl_link_train_1()
1443 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); in msm_dp_ctrl_link_train_1()
1448 old_v_level = ctrl->link->phy_params.v_level; in msm_dp_ctrl_link_train_1()
1452 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status); in msm_dp_ctrl_link_train_1()
1457 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_1()
1461 if (ctrl->link->phy_params.v_level >= in msm_dp_ctrl_link_train_1()
1467 if (old_v_level != ctrl->link->phy_params.v_level) { in msm_dp_ctrl_link_train_1()
1469 old_v_level = ctrl->link->phy_params.v_level; in msm_dp_ctrl_link_train_1()
1472 msm_dp_link_adjust_levels(ctrl->link, link_status); in msm_dp_ctrl_link_train_1()
1473 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); in msm_dp_ctrl_link_train_1()
1482 static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_link_rate_down_shift() argument
1485 struct msm_dp_link_info *link_params = &ctrl->link->link_params; in msm_dp_ctrl_link_rate_down_shift()
1509 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n", in msm_dp_ctrl_link_rate_down_shift()
1516 static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_link_lane_down_shift() argument
1519 if (ctrl->link->link_params.num_lanes == 1) in msm_dp_ctrl_link_lane_down_shift()
1522 ctrl->link->link_params.num_lanes /= 2; in msm_dp_ctrl_link_lane_down_shift()
1523 ctrl->link->link_params.rate = ctrl->panel->link_info.rate; in msm_dp_ctrl_link_lane_down_shift()
1525 ctrl->link->phy_params.p_level = 0; in msm_dp_ctrl_link_lane_down_shift()
1526 ctrl->link->phy_params.v_level = 0; in msm_dp_ctrl_link_lane_down_shift()
1531 static void msm_dp_ctrl_clear_training_pattern(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_clear_training_pattern() argument
1536 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE, dp_phy); in msm_dp_ctrl_clear_training_pattern()
1538 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, in msm_dp_ctrl_clear_training_pattern()
1539 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_clear_training_pattern()
1543 static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_link_train_2() argument
1553 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, in msm_dp_ctrl_link_train_2()
1554 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_2()
1556 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_link_train_2()
1560 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1563 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1571 ret = msm_dp_ctrl_set_pattern_state_bit(ctrl, state_ctrl_bit); in msm_dp_ctrl_link_train_2()
1575 msm_dp_ctrl_train_pattern_set(ctrl, pattern, dp_phy); in msm_dp_ctrl_link_train_2()
1580 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status); in msm_dp_ctrl_link_train_2()
1585 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_2()
1589 msm_dp_link_adjust_levels(ctrl->link, link_status); in msm_dp_ctrl_link_train_2()
1590 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); in msm_dp_ctrl_link_train_2()
1599 static int msm_dp_ctrl_link_train_1_2(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_link_train_1_2() argument
1604 ret = msm_dp_ctrl_link_train_1(ctrl, training_step, dp_phy); in msm_dp_ctrl_link_train_1_2()
1609 drm_dbg_dp(ctrl->drm_dev, "link training #1 on phy %d successful\n", dp_phy); in msm_dp_ctrl_link_train_1_2()
1611 ret = msm_dp_ctrl_link_train_2(ctrl, training_step, dp_phy); in msm_dp_ctrl_link_train_1_2()
1616 drm_dbg_dp(ctrl->drm_dev, "link training #2 on phy %d successful\n", dp_phy); in msm_dp_ctrl_link_train_1_2()
1621 static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_link_train() argument
1626 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_link_train()
1631 msm_dp_ctrl_config_ctrl(ctrl); in msm_dp_ctrl_link_train()
1633 link_info.num_lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_link_train()
1634 link_info.rate = ctrl->link->link_params.rate; in msm_dp_ctrl_link_train()
1637 msm_dp_aux_link_configure(ctrl->aux, &link_info); in msm_dp_ctrl_link_train()
1643 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2); in msm_dp_ctrl_link_train()
1647 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, in msm_dp_ctrl_link_train()
1651 for (i = ctrl->link->lttpr_count - 1; i >= 0; i--) { in msm_dp_ctrl_link_train()
1654 ret = msm_dp_ctrl_link_train_1_2(ctrl, training_step, dp_phy); in msm_dp_ctrl_link_train()
1655 msm_dp_ctrl_clear_training_pattern(ctrl, dp_phy); in msm_dp_ctrl_link_train()
1666 ret = msm_dp_ctrl_link_train_1_2(ctrl, training_step, DP_PHY_DPRX); in msm_dp_ctrl_link_train()
1673 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_link_train()
1678 static int msm_dp_ctrl_setup_main_link(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_setup_main_link() argument
1683 msm_dp_ctrl_mainlink_enable(ctrl); in msm_dp_ctrl_setup_main_link()
1685 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) in msm_dp_ctrl_setup_main_link()
1694 ret = msm_dp_ctrl_link_train(ctrl, training_step); in msm_dp_ctrl_setup_main_link()
1701 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_core_clk_enable() local
1704 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_core_clk_enable()
1706 if (ctrl->core_clks_on) { in msm_dp_ctrl_core_clk_enable()
1707 drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n"); in msm_dp_ctrl_core_clk_enable()
1711 ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks); in msm_dp_ctrl_core_clk_enable()
1715 ctrl->core_clks_on = true; in msm_dp_ctrl_core_clk_enable()
1717 drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n"); in msm_dp_ctrl_core_clk_enable()
1718 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_core_clk_enable()
1719 str_on_off(ctrl->stream_clks_on), in msm_dp_ctrl_core_clk_enable()
1720 str_on_off(ctrl->link_clks_on), in msm_dp_ctrl_core_clk_enable()
1721 str_on_off(ctrl->core_clks_on)); in msm_dp_ctrl_core_clk_enable()
1728 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_core_clk_disable() local
1730 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_core_clk_disable()
1732 clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks); in msm_dp_ctrl_core_clk_disable()
1734 ctrl->core_clks_on = false; in msm_dp_ctrl_core_clk_disable()
1736 drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n"); in msm_dp_ctrl_core_clk_disable()
1737 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_core_clk_disable()
1738 str_on_off(ctrl->stream_clks_on), in msm_dp_ctrl_core_clk_disable()
1739 str_on_off(ctrl->link_clks_on), in msm_dp_ctrl_core_clk_disable()
1740 str_on_off(ctrl->core_clks_on)); in msm_dp_ctrl_core_clk_disable()
1745 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_link_clk_enable() local
1748 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_link_clk_enable()
1750 if (ctrl->link_clks_on) { in msm_dp_ctrl_link_clk_enable()
1751 drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n"); in msm_dp_ctrl_link_clk_enable()
1755 if (!ctrl->core_clks_on) { in msm_dp_ctrl_link_clk_enable()
1756 drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n"); in msm_dp_ctrl_link_clk_enable()
1761 ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks); in msm_dp_ctrl_link_clk_enable()
1765 ctrl->link_clks_on = true; in msm_dp_ctrl_link_clk_enable()
1767 drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n"); in msm_dp_ctrl_link_clk_enable()
1768 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_link_clk_enable()
1769 str_on_off(ctrl->stream_clks_on), in msm_dp_ctrl_link_clk_enable()
1770 str_on_off(ctrl->link_clks_on), in msm_dp_ctrl_link_clk_enable()
1771 str_on_off(ctrl->core_clks_on)); in msm_dp_ctrl_link_clk_enable()
1778 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_link_clk_disable() local
1780 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_link_clk_disable()
1782 clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks); in msm_dp_ctrl_link_clk_disable()
1784 ctrl->link_clks_on = false; in msm_dp_ctrl_link_clk_disable()
1786 drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n"); in msm_dp_ctrl_link_clk_disable()
1787 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_link_clk_disable()
1788 str_on_off(ctrl->stream_clks_on), in msm_dp_ctrl_link_clk_disable()
1789 str_on_off(ctrl->link_clks_on), in msm_dp_ctrl_link_clk_disable()
1790 str_on_off(ctrl->core_clks_on)); in msm_dp_ctrl_link_clk_disable()
1793 static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_enable_mainlink_clocks() argument
1796 struct phy *phy = ctrl->phy; in msm_dp_ctrl_enable_mainlink_clocks()
1797 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_enable_mainlink_clocks()
1799 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_enable_mainlink_clocks()
1800 ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; in msm_dp_ctrl_enable_mainlink_clocks()
1801 ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); in msm_dp_ctrl_enable_mainlink_clocks()
1803 phy_configure(phy, &ctrl->phy_opts); in msm_dp_ctrl_enable_mainlink_clocks()
1806 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); in msm_dp_ctrl_enable_mainlink_clocks()
1807 ret = msm_dp_ctrl_link_clk_enable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_enable_mainlink_clocks()
1811 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate); in msm_dp_ctrl_enable_mainlink_clocks()
1816 static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_enable_sdp() argument
1819 msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP); in msm_dp_ctrl_enable_sdp()
1820 msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0); in msm_dp_ctrl_enable_sdp()
1823 static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_psr_enter() argument
1827 cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); in msm_dp_ctrl_psr_enter()
1832 msm_dp_ctrl_enable_sdp(ctrl); in msm_dp_ctrl_psr_enter()
1833 msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); in msm_dp_ctrl_psr_enter()
1836 static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_psr_exit() argument
1840 cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); in msm_dp_ctrl_psr_exit()
1845 msm_dp_ctrl_enable_sdp(ctrl); in msm_dp_ctrl_psr_exit()
1846 msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); in msm_dp_ctrl_psr_exit()
1851 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, in msm_dp_ctrl_config_psr() local
1855 if (!ctrl->panel->psr_cap.version) in msm_dp_ctrl_config_psr()
1859 cfg = msm_dp_read_link(ctrl, REG_PSR_CONFIG); in msm_dp_ctrl_config_psr()
1861 msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg); in msm_dp_ctrl_config_psr()
1863 msm_dp_ctrl_config_psr_interrupt(ctrl); in msm_dp_ctrl_config_psr()
1864 msm_dp_ctrl_enable_sdp(ctrl); in msm_dp_ctrl_config_psr()
1867 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); in msm_dp_ctrl_config_psr()
1872 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, in msm_dp_ctrl_set_psr() local
1875 if (!ctrl->panel->psr_cap.version) in msm_dp_ctrl_set_psr()
1889 reinit_completion(&ctrl->psr_op_comp); in msm_dp_ctrl_set_psr()
1890 msm_dp_ctrl_psr_enter(ctrl); in msm_dp_ctrl_set_psr()
1892 if (!wait_for_completion_timeout(&ctrl->psr_op_comp, in msm_dp_ctrl_set_psr()
1895 msm_dp_ctrl_psr_exit(ctrl); in msm_dp_ctrl_set_psr()
1900 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_set_psr()
1902 msm_dp_ctrl_psr_mainlink_disable(ctrl); in msm_dp_ctrl_set_psr()
1904 msm_dp_ctrl_psr_mainlink_enable(ctrl); in msm_dp_ctrl_set_psr()
1906 msm_dp_ctrl_psr_exit(ctrl); in msm_dp_ctrl_set_psr()
1907 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); in msm_dp_ctrl_set_psr()
1908 msm_dp_ctrl_wait4video_ready(ctrl); in msm_dp_ctrl_set_psr()
1909 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_set_psr()
1913 static void msm_dp_ctrl_phy_reset(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_phy_reset() argument
1915 msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, in msm_dp_ctrl_phy_reset()
1918 msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, 0x0); in msm_dp_ctrl_phy_reset()
1923 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_phy_init() local
1926 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_phy_init()
1927 phy = ctrl->phy; in msm_dp_ctrl_phy_init()
1929 msm_dp_ctrl_phy_reset(ctrl); in msm_dp_ctrl_phy_init()
1932 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_phy_init()
1938 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_phy_exit() local
1941 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_phy_exit()
1942 phy = ctrl->phy; in msm_dp_ctrl_phy_exit()
1944 msm_dp_ctrl_phy_reset(ctrl); in msm_dp_ctrl_phy_exit()
1946 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_phy_exit()
1950 static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_reinitialize_mainlink() argument
1952 struct phy *phy = ctrl->phy; in msm_dp_ctrl_reinitialize_mainlink()
1955 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_reinitialize_mainlink()
1956 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_reinitialize_mainlink()
1957 phy_configure(phy, &ctrl->phy_opts); in msm_dp_ctrl_reinitialize_mainlink()
1963 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_reinitialize_mainlink()
1965 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_reinitialize_mainlink()
1971 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); in msm_dp_ctrl_reinitialize_mainlink()
1980 static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_deinitialize_mainlink() argument
1984 phy = ctrl->phy; in msm_dp_ctrl_deinitialize_mainlink()
1986 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_deinitialize_mainlink()
1988 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_deinitialize_mainlink()
1990 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_deinitialize_mainlink()
1991 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_deinitialize_mainlink()
1999 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_deinitialize_mainlink()
2004 static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_link_maintenance() argument
2009 msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_link_maintenance()
2011 ctrl->link->phy_params.p_level = 0; in msm_dp_ctrl_link_maintenance()
2012 ctrl->link->phy_params.v_level = 0; in msm_dp_ctrl_link_maintenance()
2014 ret = msm_dp_ctrl_setup_main_link(ctrl, &training_step); in msm_dp_ctrl_link_maintenance()
2018 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_link_maintenance()
2020 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); in msm_dp_ctrl_link_maintenance()
2022 ret = msm_dp_ctrl_wait4video_ready(ctrl); in msm_dp_ctrl_link_maintenance()
2029 static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_send_phy_pattern() argument
2035 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0); in msm_dp_ctrl_send_phy_pattern()
2037 drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); in msm_dp_ctrl_send_phy_pattern()
2040 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2046 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, in msm_dp_ctrl_send_phy_pattern()
2049 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, in msm_dp_ctrl_send_phy_pattern()
2051 msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, in msm_dp_ctrl_send_phy_pattern()
2053 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2058 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2063 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2066 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, in msm_dp_ctrl_send_phy_pattern()
2069 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, in msm_dp_ctrl_send_phy_pattern()
2072 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, in msm_dp_ctrl_send_phy_pattern()
2077 value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_send_phy_pattern()
2079 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); in msm_dp_ctrl_send_phy_pattern()
2082 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, in msm_dp_ctrl_send_phy_pattern()
2085 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, in msm_dp_ctrl_send_phy_pattern()
2087 msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, in msm_dp_ctrl_send_phy_pattern()
2089 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2091 value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_send_phy_pattern()
2093 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); in msm_dp_ctrl_send_phy_pattern()
2097 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, in msm_dp_ctrl_send_phy_pattern()
2099 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2104 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_send_phy_pattern()
2110 static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_send_phy_test_pattern() argument
2114 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; in msm_dp_ctrl_send_phy_test_pattern()
2116 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); in msm_dp_ctrl_send_phy_test_pattern()
2118 if (msm_dp_ctrl_set_vx_px(ctrl, in msm_dp_ctrl_send_phy_test_pattern()
2119 ctrl->link->phy_params.v_level, in msm_dp_ctrl_send_phy_test_pattern()
2120 ctrl->link->phy_params.p_level)) { in msm_dp_ctrl_send_phy_test_pattern()
2124 msm_dp_ctrl_send_phy_pattern(ctrl, pattern_requested); in msm_dp_ctrl_send_phy_test_pattern()
2125 msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_send_phy_test_pattern()
2126 msm_dp_link_send_test_response(ctrl->link); in msm_dp_ctrl_send_phy_test_pattern()
2128 pattern_sent = msm_dp_read_link(ctrl, REG_DP_MAINLINK_READY); in msm_dp_ctrl_send_phy_test_pattern()
2157 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n", in msm_dp_ctrl_send_phy_test_pattern()
2162 static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_process_phy_test_request() argument
2167 if (!ctrl->link->phy_params.phy_test_pattern_sel) { in msm_dp_ctrl_process_phy_test_request()
2168 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_process_phy_test_request()
2178 msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_process_phy_test_request()
2180 ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_process_phy_test_request()
2186 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_process_phy_test_request()
2187 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_process_phy_test_request()
2193 if (ctrl->stream_clks_on) { in msm_dp_ctrl_process_phy_test_request()
2194 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); in msm_dp_ctrl_process_phy_test_request()
2196 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_process_phy_test_request()
2201 ctrl->stream_clks_on = true; in msm_dp_ctrl_process_phy_test_request()
2204 msm_dp_ctrl_send_phy_test_pattern(ctrl); in msm_dp_ctrl_process_phy_test_request()
2211 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_handle_sink_request() local
2219 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_handle_sink_request()
2220 sink_request = ctrl->link->sink_request; in msm_dp_ctrl_handle_sink_request()
2223 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); in msm_dp_ctrl_handle_sink_request()
2224 if (msm_dp_ctrl_process_phy_test_request(ctrl)) { in msm_dp_ctrl_handle_sink_request()
2231 if (msm_dp_ctrl_link_maintenance(ctrl)) { in msm_dp_ctrl_handle_sink_request()
2238 msm_dp_link_send_test_response(ctrl->link); in msm_dp_ctrl_handle_sink_request()
2239 if (msm_dp_ctrl_link_maintenance(ctrl)) { in msm_dp_ctrl_handle_sink_request()
2265 static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_channel_eq_ok() argument
2268 int num_lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_channel_eq_ok()
2270 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); in msm_dp_ctrl_channel_eq_ok()
2278 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_on_link() local
2289 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_on_link()
2291 rate = ctrl->panel->link_info.rate; in msm_dp_ctrl_on_link()
2292 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_on_link()
2294 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_on_link()
2296 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { in msm_dp_ctrl_on_link()
2297 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_on_link()
2302 ctrl->link->link_params.rate = rate; in msm_dp_ctrl_on_link()
2303 ctrl->link->link_params.num_lanes = in msm_dp_ctrl_on_link()
2304 ctrl->panel->link_info.num_lanes; in msm_dp_ctrl_on_link()
2305 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) in msm_dp_ctrl_on_link()
2309 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", in msm_dp_ctrl_on_link()
2310 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, in msm_dp_ctrl_on_link()
2313 rc = msm_dp_ctrl_enable_mainlink_clocks(ctrl); in msm_dp_ctrl_on_link()
2319 rc = msm_dp_ctrl_setup_main_link(ctrl, &training_step); in msm_dp_ctrl_on_link()
2325 if (!msm_dp_aux_is_link_connected(ctrl->aux)) in msm_dp_ctrl_on_link()
2328 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); in msm_dp_ctrl_on_link()
2330 rc = msm_dp_ctrl_link_rate_down_shift(ctrl); in msm_dp_ctrl_on_link()
2333 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_on_link()
2338 rc = msm_dp_ctrl_link_lane_down_shift(ctrl); in msm_dp_ctrl_on_link()
2350 if (!msm_dp_aux_is_link_connected(ctrl->aux)) in msm_dp_ctrl_on_link()
2353 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); in msm_dp_ctrl_on_link()
2356 ctrl->link->link_params.num_lanes)) in msm_dp_ctrl_on_link()
2357 rc = msm_dp_ctrl_link_rate_down_shift(ctrl); in msm_dp_ctrl_on_link()
2359 rc = msm_dp_ctrl_link_lane_down_shift(ctrl); in msm_dp_ctrl_on_link()
2367 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_on_link()
2370 rc = msm_dp_ctrl_reinitialize_mainlink(ctrl); in msm_dp_ctrl_on_link()
2377 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) in msm_dp_ctrl_on_link()
2391 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_on_link()
2393 msm_dp_ctrl_deinitialize_mainlink(ctrl); in msm_dp_ctrl_on_link()
2400 static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_link_retrain() argument
2404 return msm_dp_ctrl_setup_main_link(ctrl, &training_step); in msm_dp_ctrl_link_retrain()
2407 static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_config_msa() argument
2470 drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); in msm_dp_ctrl_config_msa()
2471 msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid); in msm_dp_ctrl_config_msa()
2472 msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); in msm_dp_ctrl_config_msa()
2479 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_on_stream() local
2486 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_on_stream()
2488 pixel_rate = pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_on_stream()
2490 if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) in msm_dp_ctrl_on_stream()
2493 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", in msm_dp_ctrl_on_stream()
2494 ctrl->link->link_params.rate, in msm_dp_ctrl_on_stream()
2495 ctrl->link->link_params.num_lanes, pixel_rate); in msm_dp_ctrl_on_stream()
2497 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_on_stream()
2499 ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); in msm_dp_ctrl_on_stream()
2501 if (!ctrl->link_clks_on) { /* link clk is off */ in msm_dp_ctrl_on_stream()
2502 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); in msm_dp_ctrl_on_stream()
2509 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_on_stream()
2515 if (ctrl->stream_clks_on) { in msm_dp_ctrl_on_stream()
2516 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); in msm_dp_ctrl_on_stream()
2518 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_on_stream()
2523 ctrl->stream_clks_on = true; in msm_dp_ctrl_on_stream()
2526 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) in msm_dp_ctrl_on_stream()
2527 msm_dp_ctrl_link_retrain(ctrl); in msm_dp_ctrl_on_stream()
2530 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_on_stream()
2536 reinit_completion(&ctrl->video_comp); in msm_dp_ctrl_on_stream()
2538 msm_dp_ctrl_configure_source_params(ctrl); in msm_dp_ctrl_on_stream()
2540 msm_dp_ctrl_config_msa(ctrl, in msm_dp_ctrl_on_stream()
2541 ctrl->link->link_params.rate, in msm_dp_ctrl_on_stream()
2543 ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); in msm_dp_ctrl_on_stream()
2545 msm_dp_panel_clear_dsc_dto(ctrl->panel); in msm_dp_ctrl_on_stream()
2547 msm_dp_ctrl_setup_tr_unit(ctrl); in msm_dp_ctrl_on_stream()
2549 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); in msm_dp_ctrl_on_stream()
2551 ret = msm_dp_ctrl_wait4video_ready(ctrl); in msm_dp_ctrl_on_stream()
2555 mainlink_ready = msm_dp_ctrl_mainlink_ready(ctrl); in msm_dp_ctrl_on_stream()
2556 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_on_stream()
2565 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_off_link_stream() local
2568 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_off_link_stream()
2569 phy = ctrl->phy; in msm_dp_ctrl_off_link_stream()
2571 msm_dp_panel_disable_vsc_sdp(ctrl->panel); in msm_dp_ctrl_off_link_stream()
2574 msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); in msm_dp_ctrl_off_link_stream()
2576 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_off_link_stream()
2578 if (ctrl->stream_clks_on) { in msm_dp_ctrl_off_link_stream()
2579 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off_link_stream()
2580 ctrl->stream_clks_on = false; in msm_dp_ctrl_off_link_stream()
2583 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_off_link_stream()
2584 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off_link_stream()
2592 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_off_link_stream()
2598 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_off_link() local
2601 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_off_link()
2602 phy = ctrl->phy; in msm_dp_ctrl_off_link()
2604 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_off_link()
2606 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_off_link()
2607 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off_link()
2620 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_off() local
2623 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_off()
2624 phy = ctrl->phy; in msm_dp_ctrl_off()
2626 msm_dp_panel_disable_vsc_sdp(ctrl->panel); in msm_dp_ctrl_off()
2628 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_off()
2630 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off()
2632 if (ctrl->stream_clks_on) { in msm_dp_ctrl_off()
2633 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off()
2634 ctrl->stream_clks_on = false; in msm_dp_ctrl_off()
2637 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_off()
2638 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off()
2641 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_off()
2647 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_isr() local
2654 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_isr()
2656 if (ctrl->panel->psr_cap.version) { in msm_dp_ctrl_isr()
2657 isr = msm_dp_ctrl_get_psr_interrupt(ctrl); in msm_dp_ctrl_isr()
2660 complete(&ctrl->psr_op_comp); in msm_dp_ctrl_isr()
2663 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n"); in msm_dp_ctrl_isr()
2666 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n"); in msm_dp_ctrl_isr()
2669 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n"); in msm_dp_ctrl_isr()
2672 isr = msm_dp_ctrl_get_interrupt(ctrl); in msm_dp_ctrl_isr()
2675 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n"); in msm_dp_ctrl_isr()
2676 complete(&ctrl->video_comp); in msm_dp_ctrl_isr()
2681 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n"); in msm_dp_ctrl_isr()
2682 complete(&ctrl->idle_comp); in msm_dp_ctrl_isr()
2687 isr = msm_dp_ctrl_get_aux_interrupt(ctrl); in msm_dp_ctrl_isr()
2689 ret |= msm_dp_aux_isr(ctrl->aux, isr); in msm_dp_ctrl_isr()
2706 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_clk_init() local
2710 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_clk_init()
2711 dev = ctrl->dev; in msm_dp_ctrl_clk_init()
2713 ctrl->num_core_clks = ARRAY_SIZE(core_clks); in msm_dp_ctrl_clk_init()
2714 ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL); in msm_dp_ctrl_clk_init()
2715 if (!ctrl->core_clks) in msm_dp_ctrl_clk_init()
2718 for (i = 0; i < ctrl->num_core_clks; i++) in msm_dp_ctrl_clk_init()
2719 ctrl->core_clks[i].id = core_clks[i]; in msm_dp_ctrl_clk_init()
2721 rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks); in msm_dp_ctrl_clk_init()
2725 ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks); in msm_dp_ctrl_clk_init()
2726 ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL); in msm_dp_ctrl_clk_init()
2727 if (!ctrl->link_clks) in msm_dp_ctrl_clk_init()
2730 for (i = 0; i < ctrl->num_link_clks; i++) in msm_dp_ctrl_clk_init()
2731 ctrl->link_clks[i].id = ctrl_clks[i]; in msm_dp_ctrl_clk_init()
2733 rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks); in msm_dp_ctrl_clk_init()
2737 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); in msm_dp_ctrl_clk_init()
2738 if (IS_ERR(ctrl->pixel_clk)) in msm_dp_ctrl_clk_init()
2739 return PTR_ERR(ctrl->pixel_clk); in msm_dp_ctrl_clk_init()
2750 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_get() local
2758 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); in msm_dp_ctrl_get()
2759 if (!ctrl) { in msm_dp_ctrl_get()
2776 init_completion(&ctrl->idle_comp); in msm_dp_ctrl_get()
2777 init_completion(&ctrl->psr_op_comp); in msm_dp_ctrl_get()
2778 init_completion(&ctrl->video_comp); in msm_dp_ctrl_get()
2781 ctrl->panel = panel; in msm_dp_ctrl_get()
2782 ctrl->aux = aux; in msm_dp_ctrl_get()
2783 ctrl->link = link; in msm_dp_ctrl_get()
2784 ctrl->dev = dev; in msm_dp_ctrl_get()
2785 ctrl->phy = phy; in msm_dp_ctrl_get()
2786 ctrl->ahb_base = ahb_base; in msm_dp_ctrl_get()
2787 ctrl->link_base = link_base; in msm_dp_ctrl_get()
2789 ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_get()
2795 return &ctrl->msm_dp_ctrl; in msm_dp_ctrl_get()