disp/mdp5/mdp5_crtc.c

20 #include "mdp5_kms.h"
71 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
169 	struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
170 	struct msm_kms *kms = &mdp5_kms->base.base;
216 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
330 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm,
332 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
334 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
337 			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm,
339 			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm,
341 			mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm,
346 	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
347 	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm),
350 		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
351 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm),
365 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
385 	mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm),
390 	val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm));
392 	mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val);
397 		mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm),
402 		val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm));
404 		mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val);
492 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
493 	struct device *dev = &mdp5_kms->pdev->dev;
505 		mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
507 	mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
512 		spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags);
515 		spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags);
538 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
539 	struct device *dev = &mdp5_kms->pdev->dev;
573 	mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
576 		mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
699 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
743 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
884 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
924 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
925 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
927 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
930 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
933 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm),
936 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm),
939 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm),
944 	mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
955 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
956 	struct platform_device *pdev = mdp5_kms->pdev;
957 	struct msm_kms *kms = &mdp5_kms->base.base;
1038 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
1067 	pm_runtime_get_sync(&mdp5_kms->pdev->dev);
1075 	pm_runtime_put_sync(&mdp5_kms->pdev->dev);
1086 	struct mdp5_kms *mdp5_kms = get_kms(state->crtc);
1097 	if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
1268 	struct mdp5_kms *mdp5_kms = get_kms(crtc);
1271 	mdp_irq_update(&mdp5_kms->base);