msm/adreno/a5xx_power.c

103 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq)
105 	struct drm_device *dev = gpu->dev;
122 static void a530_lm_setup(struct msm_gpu *gpu)
124 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
130 		gpu_write(gpu, a5xx_sequence_regs[i].reg,
134 	gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007);
135 	gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01);
136 	gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01);
139 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);
141 	gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage);
144 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);
146 	gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);
147 	gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1);
150 	gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);
151 	gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1);
153 	gpu_write(gpu, AGC_MSG_STATE, 1);
154 	gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID);
157 	gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);
158 	gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1);
164 	gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate));
165 	gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000);
167 	gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, 4 * sizeof(uint32_t));
168 	gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
175 static void a540_lm_setup(struct msm_gpu *gpu)
177 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
188 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);
191 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);
193 	gpu_write(gpu, AGC_MSG_STATE, 0x80000001);
194 	gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID);
196 	gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);
197 	gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1);
199 	gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate));
200 	gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000);
202 	gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LM_CONFIG), config);
203 	gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LEVEL_CONFIG), LEVEL_CONFIG);
204 	gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE,
207 	gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
211 static void a5xx_pc_init(struct msm_gpu *gpu)
213 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x7F);
214 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_BINNING_CTRL, 0);
215 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST, 0xA0080);
216 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY, 0x600040);
220 static int a5xx_gpmu_init(struct msm_gpu *gpu)
222 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
224 	struct msm_ringbuffer *ring = gpu->rb[0];
243 	a5xx_flush(gpu, ring, true);
245 	if (!a5xx_idle(gpu, ring)) {
247 			gpu->name);
252 		gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014);
255 	gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0);
261 	if (spin_usecs(gpu, 25, REG_A5XX_GPMU_GENERAL_0, 0xFFFFFFFF,
264 			gpu->name);
267 		u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1);
271 				  gpu->name, val);
278 static void a5xx_lm_enable(struct msm_gpu *gpu)
280 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
286 	gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0);
287 	gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A);
288 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01);
289 	gpu_write(gpu, REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK, 0x50000);
290 	gpu_write(gpu, REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL, 0x30000);
292 	gpu_write(gpu, REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL, 0x011);
295 int a5xx_power_init(struct msm_gpu *gpu)
297 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
306 		a530_lm_setup(gpu);
308 		a540_lm_setup(gpu);
311 	a5xx_pc_init(gpu);
314 	ret = a5xx_gpmu_init(gpu);
319 	a5xx_lm_enable(gpu);
324 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
326 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
328 	struct drm_device *drm = gpu->dev;
366 		MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->vm,