drm/mediatek/mtk_hdmi_ddc.c

64 static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
67 	writel(readl(ddc->regs + offset) | val, ddc->regs + offset);
70 static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,
73 	writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);
76 static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset,
79 	return (readl(ddc->regs + offset) & val) == val;
82 static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset,
88 	tmp = readl(ddc->regs + offset);
91 	writel(tmp, ddc->regs + offset);
94 static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc,
98 	return (readl(ddc->regs + offset) & mask) >> shift;
101 static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode)
105 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,
107 	sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);
108 	readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,
112 static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
114 	struct device *dev = ddc->adap.dev.parent;
120 	ddcm_trigger_mode(ddc, DDCM_START);
121 	sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);
122 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
124 	ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
125 	ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
146 		sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,
148 		ddcm_trigger_mode(ddc, (ack_final == 1) ?
152 		ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,
175 			msg->buf[index + i - 1] = sif_read_mask(ddc, offset,
187 static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)
189 	struct device *dev = ddc->adap.dev.parent;
192 	ddcm_trigger_mode(ddc, DDCM_START);
193 	sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);
194 	sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);
195 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,
197 	ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);
199 	ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);
213 	struct mtk_hdmi_ddc *ddc = adapter->algo_data;
218 	if (!ddc) {
223 	sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);
224 	sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);
225 	sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);
227 	if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {
228 		dev_err(dev, "ddc line is busy!\n");
232 	sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,
242 			ret = mtk_hdmi_ddc_read_msg(ddc, msg);
244 			ret = mtk_hdmi_ddc_write_msg(ddc, msg);
249 	ddcm_trigger_mode(ddc, DDCM_STOP);
254 	ddcm_trigger_mode(ddc, DDCM_STOP);
255 	dev_err(dev, "ddc failed!\n");
272 	struct mtk_hdmi_ddc *ddc;
276 	ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL);
277 	if (!ddc)
280 	ddc->clk = devm_clk_get(dev, "ddc-i2c");
281 	if (IS_ERR(ddc->clk))
282 		return dev_err_probe(dev, PTR_ERR(ddc->clk),
285 	ddc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
286 	if (IS_ERR(ddc->regs))
287 		return PTR_ERR(ddc->regs);
289 	ret = clk_prepare_enable(ddc->clk);
291 		return dev_err_probe(dev, ret, "enable ddc clk failed!\n");
293 	strscpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name));
294 	ddc->adap.owner = THIS_MODULE;
295 	ddc->adap.algo = &mtk_hdmi_ddc_algorithm;
296 	ddc->adap.retries = 3;
297 	ddc->adap.dev.of_node = dev->of_node;
298 	ddc->adap.algo_data = ddc;
299 	ddc->adap.dev.parent = &pdev->dev;
301 	ret = i2c_add_adapter(&ddc->adap);
303 		clk_disable_unprepare(ddc->clk);
307 	platform_set_drvdata(pdev, ddc);
309 	dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap);
310 	dev_dbg(dev, "ddc->clk: %p\n", ddc->clk);
319 	struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev);
321 	i2c_del_adapter(&ddc->adap);
322 	clk_disable_unprepare(ddc->clk);
326 	{ .compatible = "mediatek,mt8173-hdmi-ddc", },
335 		.name = "mediatek-hdmi-ddc",