drm/ingenic/ingenic-ipu.c

9 #include "ingenic-ipu.h"
43 	void (*set_coefs)(struct ingenic_ipu *ipu, unsigned int reg,
155 static void jz4760_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
199 	regmap_write(ipu->map, reg, val);
204 	regmap_write(ipu->map, reg, val);
207 static void jz4725b_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
223 	regmap_write(ipu->map, reg, val);
227 			regmap_write(ipu->map, reg, JZ4725B_IPU_RSZ_LUT_IN_EN);
231 static void ingenic_ipu_set_downscale_coefs(struct ingenic_ipu *ipu,
244 		ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
249 static void ingenic_ipu_set_integer_upscale_coefs(struct ingenic_ipu *ipu,
260 		ipu->soc_info->set_coefs(ipu, reg, 0, false, 512, i == num - 1);
263 static void ingenic_ipu_set_upscale_coefs(struct ingenic_ipu *ipu,
278 		ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
283 static void ingenic_ipu_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
287 	regmap_write(ipu->map, reg, -1);
290 		ingenic_ipu_set_downscale_coefs(ipu, reg, num, denom);
292 		ingenic_ipu_set_integer_upscale_coefs(ipu, reg, num);
294 		ingenic_ipu_set_upscale_coefs(ipu, reg, num, denom);
326 	struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
338 	ipu_state = ingenic_ipu_get_new_priv_state(ipu, state);
344 	if (!ipu->clk_enabled) {
345 		err = clk_enable(ipu->clk);
347 			dev_err(ipu->dev, "Unable to enable clock: %d\n", err);
351 		ipu->clk_enabled = true;
357 		regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RST);
360 		regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
364 	if (ingenic_drm_map_noncoherent(ipu->master))
365 		drm_fb_dma_sync_non_coherent(ipu->drm, oldstate, newstate);
368 	ipu->addr_y = drm_fb_dma_get_gem_addr(newstate->fb, newstate, 0);
370 		ipu->addr_u = drm_fb_dma_get_gem_addr(newstate->fb, newstate,
373 		ipu->addr_v = drm_fb_dma_get_gem_addr(newstate->fb, newstate,
380 	regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
381 	regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
382 	regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
385 		regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_SPKG_SEL);
387 	ingenic_drm_plane_config(ipu->master, plane, DRM_FORMAT_XRGB8888);
398 	regmap_write(ipu->map, JZ_REG_IPU_UV_STRIDE, stride);
401 	regmap_write(ipu->map, JZ_REG_IPU_Y_STRIDE, stride);
403 	regmap_write(ipu->map, JZ_REG_IPU_IN_GS,
470 	regmap_write(ipu->map, JZ_REG_IPU_D_FMT, format);
473 	regmap_write(ipu->map, JZ_REG_IPU_OUT_GS,
476 	regmap_write(ipu->map, JZ_REG_IPU_OUT_STRIDE, newstate->crtc_w * 4);
479 		regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CSC_EN);
487 		regmap_write(ipu->map, JZ_REG_IPU_CSC_OFFSET,
497 		regmap_write(ipu->map, JZ_REG_IPU_CSC_C0_COEF, 0x4a8);
498 		regmap_write(ipu->map, JZ_REG_IPU_CSC_C1_COEF, 0x662);
499 		regmap_write(ipu->map, JZ_REG_IPU_CSC_C2_COEF, 0x191);
500 		regmap_write(ipu->map, JZ_REG_IPU_CSC_C3_COEF, 0x341);
501 		regmap_write(ipu->map, JZ_REG_IPU_CSC_C4_COEF, 0x811);
511 	if (ipu->soc_info->has_bicubic)
519 		if (!ipu->soc_info->has_bicubic && !upscaling_w)
531 		if (!ipu->soc_info->has_bicubic && !upscaling_h)
538 	regmap_update_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_ZOOM_SEL |
543 	regmap_write(ipu->map, JZ_REG_IPU_RSZ_COEF_INDEX, coef_index);
546 		ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_HRSZ_COEF_LUT,
550 		ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_VRSZ_COEF_LUT,
554 	regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
557 	regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
560 	dev_dbg(ipu->dev, "Scaling %ux%u to %ux%u (%u:%u horiz, %u:%u vert)\n",
575 	struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
587 	ipu_state = ingenic_ipu_get_priv_state(ipu, state);
649 	if (ingenic_drm_map_noncoherent(ipu->master))
658 	struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
660 	regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_STOP);
661 	regmap_clear_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CHIP_EN);
663 	ingenic_drm_plane_disable(ipu->master, plane);
665 	if (ipu->clk_enabled) {
666 		clk_disable(ipu->clk);
667 		ipu->clk_enabled = false;
682 	struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
684 	if (property != ipu->sharpness_prop)
687 	*val = ipu->sharpness;
697 	struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
701 	if (property != ipu->sharpness_prop)
704 	mode_changed = val != ipu->sharpness;
705 	ipu->sharpness = val;
760 	struct ingenic_ipu *ipu = arg;
761 	struct drm_crtc *crtc = drm_crtc_from_index(ipu->drm, 0);
765 	if (ipu->soc_info->manual_restart)
766 		regmap_read(ipu->map, JZ_REG_IPU_STATUS, &dummy);
769 	regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
772 	regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
773 	regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
774 	regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
777 	if (ipu->soc_info->manual_restart)
778 		regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RUN);
800 	struct ingenic_ipu *ipu;
805 	ipu = devm_kzalloc(dev, sizeof(*ipu), GFP_KERNEL);
806 	if (!ipu)
815 	ipu->dev = dev;
816 	ipu->drm = drm;
817 	ipu->master = master;
818 	ipu->soc_info = soc_info;
826 	ipu->map = devm_regmap_init_mmio(dev, base, &ingenic_ipu_regmap_config);
827 	if (IS_ERR(ipu->map)) {
829 		return PTR_ERR(ipu->map);
836 	ipu->clk = devm_clk_get(dev, "ipu");
837 	if (IS_ERR(ipu->clk)) {
839 		return PTR_ERR(ipu->clk);
843 			       dev_name(dev), ipu);
849 	plane = &ipu->plane;
872 	ipu->sharpness_prop = drm_property_create_range(drm, 0, "sharpness",
874 	if (!ipu->sharpness_prop) {
880 	ipu->sharpness = soc_info->has_bicubic ? 8 : 1;
881 	drm_object_attach_property(&plane->base, ipu->sharpness_prop,
882 				   ipu->sharpness);
884 	err = clk_prepare(ipu->clk);
896 	drm_atomic_private_obj_init(drm, &ipu->private_obj, &private_state->base,
902 	clk_unprepare(ipu->clk);
909 	struct ingenic_ipu *ipu = dev_get_drvdata(dev);
911 	drm_atomic_private_obj_fini(&ipu->private_obj);
912 	clk_unprepare(ipu->clk);
982 	{ .compatible = "ingenic,jz4725b-ipu", .data = &jz4725b_soc_info },
983 	{ .compatible = "ingenic,jz4760-ipu", .data = &jz4760_soc_info },
990 		.name = "ingenic-ipu",