i915/soc/intel_dram.c

389 skl_dram_get_channels_info(struct drm_i915_private *i915, struct dram_info *dram_info)
399 		dram_info->num_channels++;
405 		dram_info->num_channels++;
407 	if (dram_info->num_channels == 0) {
417 	dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
419 	dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
422 		    str_yes_no(dram_info->symmetric_memory));
451 skl_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
455 	dram_info->type = skl_get_dram_type(i915);
457 	ret = skl_dram_get_channels_info(i915, dram_info);
542 static int bxt_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
559 		dram_info->num_channels++;
565 			    dram_info->type != INTEL_DRAM_UNKNOWN &&
566 			    dram_info->type != type);
577 			dram_info->type = type;
580 	if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
589 					  struct dram_info *dram_info)
602 			dram_info->type = INTEL_DRAM_DDR4;
605 			dram_info->type = INTEL_DRAM_DDR5;
608 			dram_info->type = INTEL_DRAM_LPDDR5;
611 			dram_info->type = INTEL_DRAM_LPDDR4;
614 			dram_info->type = INTEL_DRAM_DDR3;
617 			dram_info->type = INTEL_DRAM_LPDDR3;
626 			dram_info->type = INTEL_DRAM_DDR4;
629 			dram_info->type = INTEL_DRAM_DDR3;
632 			dram_info->type = INTEL_DRAM_LPDDR3;
635 			dram_info->type = INTEL_DRAM_LPDDR4;
643 	dram_info->num_channels = (val & 0xf0) >> 4;
644 	dram_info->num_qgv_points = (val & 0xf00) >> 8;
645 	dram_info->num_psf_gv_points = (val & 0x3000) >> 12;
650 static int gen11_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
652 	int ret = skl_get_dram_info(i915, dram_info);
657 	return icl_pcode_read_mem_global_info(i915, dram_info);
660 static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
662 	dram_info->wm_lv_0_adjust_needed = false;
664 	return icl_pcode_read_mem_global_info(i915, dram_info);
667 static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
673 		dram_info->type = INTEL_DRAM_DDR4;
676 		dram_info->type = INTEL_DRAM_DDR5;
679 		dram_info->type = INTEL_DRAM_LPDDR5;
682 		dram_info->type = INTEL_DRAM_LPDDR4;
685 		dram_info->type = INTEL_DRAM_DDR3;
688 		dram_info->type = INTEL_DRAM_LPDDR3;
692 		dram_info->type = INTEL_DRAM_GDDR;
696 		dram_info->type = INTEL_DRAM_GDDR_ECC;
703 	dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);
704 	dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
712 	struct dram_info *dram_info;
721 	dram_info = drmm_kzalloc(&i915->drm, sizeof(*dram_info), GFP_KERNEL);
722 	if (!dram_info)
725 	i915->dram_info = dram_info;
731 	dram_info->wm_lv_0_adjust_needed = !IS_BROXTON(i915) && !IS_GEMINILAKE(i915);
734 		ret = xelpdp_get_dram_info(i915, dram_info);
736 		ret = gen12_get_dram_info(i915, dram_info);
738 		ret = gen11_get_dram_info(i915, dram_info);
740 		ret = bxt_get_dram_info(i915, dram_info);
742 		ret = skl_get_dram_info(i915, dram_info);
745 		    intel_dram_type_str(dram_info->type));
751 	drm_dbg_kms(&i915->drm, "Num qgv points %u\n", dram_info->num_qgv_points);
753 	drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
756 		    str_yes_no(dram_info->wm_lv_0_adjust_needed));
766 const struct dram_info *intel_dram_info(struct drm_device *drm)
770 	return i915->dram_info;