68 		void *p_data, unsigned int bytes, bool read)  in failsafe_emulate_mmio_rw()  argument
83 					bytes);  in failsafe_emulate_mmio_rw()
86 					bytes);  in failsafe_emulate_mmio_rw()
91 			memcpy(p_data, pt, bytes);  in failsafe_emulate_mmio_rw()
93 			memcpy(pt, p_data, bytes);  in failsafe_emulate_mmio_rw()
110 		void *p_data, unsigned int bytes)  in intel_vgpu_emulate_mmio_read()  argument
118 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);  in intel_vgpu_emulate_mmio_read()
125 	if (drm_WARN_ON(&i915->drm, bytes > 8))  in intel_vgpu_emulate_mmio_read()
132 		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))  in intel_vgpu_emulate_mmio_read()
135 				!reg_is_gtt(gvt, offset + bytes - 1)))  in intel_vgpu_emulate_mmio_read()
139 				p_data, bytes);  in intel_vgpu_emulate_mmio_read()
146 		ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes);  in intel_vgpu_emulate_mmio_read()
150 	if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1)))  in intel_vgpu_emulate_mmio_read()
154 		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes)))  in intel_vgpu_emulate_mmio_read()
158 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);  in intel_vgpu_emulate_mmio_read()
168 			offset, bytes);  in intel_vgpu_emulate_mmio_read()
185 		void *p_data, unsigned int bytes)  in intel_vgpu_emulate_mmio_write()  argument
193 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);  in intel_vgpu_emulate_mmio_write()
201 	if (drm_WARN_ON(&i915->drm, bytes > 8))  in intel_vgpu_emulate_mmio_write()
208 		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))  in intel_vgpu_emulate_mmio_write()
211 				!reg_is_gtt(gvt, offset + bytes - 1)))  in intel_vgpu_emulate_mmio_write()
215 				p_data, bytes);  in intel_vgpu_emulate_mmio_write()
222 		ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes);  in intel_vgpu_emulate_mmio_write()
226 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);  in intel_vgpu_emulate_mmio_write()
235 		     bytes);  in intel_vgpu_emulate_mmio_write()