i915/gvt/mmio.c

48  * @vgpu: a vGPU
54 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
56 	u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
67 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
74 	if (!vgpu || !p_data)
77 	gvt = vgpu->gvt;
78 	mutex_lock(&vgpu->vgpu_lock);
79 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
82 			intel_vgpu_default_mmio_read(vgpu, offset, p_data,
85 			intel_vgpu_default_mmio_write(vgpu, offset, p_data,
89 		pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;
96 	mutex_unlock(&vgpu->vgpu_lock);
101  * @vgpu: a vGPU
109 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
112 	struct intel_gvt *gvt = vgpu->gvt;
117 	if (vgpu->failsafe) {
118 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
121 	mutex_lock(&vgpu->vgpu_lock);
123 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
138 		ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
146 		ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes);
158 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
170 	mutex_unlock(&vgpu->vgpu_lock);
176  * @vgpu: a vGPU
184 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
187 	struct intel_gvt *gvt = vgpu->gvt;
192 	if (vgpu->failsafe) {
193 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
197 	mutex_lock(&vgpu->vgpu_lock);
199 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
214 		ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
222 		ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes);
226 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
237 	mutex_unlock(&vgpu->vgpu_lock);
244  * @vgpu: a vGPU
247 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
249 	struct intel_gvt *gvt = vgpu->gvt;
254 		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
256 		vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
259 		vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
262 		vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
264 		if (IS_BROXTON(vgpu->gvt->gt->i915)) {
265 			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
267 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
269 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
271 			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
273 			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
275 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
277 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
280 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
282 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
285 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
287 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
290 			vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
302 		memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
309  * @vgpu: a vGPU
314 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
316 	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
318 	vgpu->mmio.vreg = vzalloc(info->mmio_size);
319 	if (!vgpu->mmio.vreg)
322 	intel_vgpu_reset_mmio(vgpu, true);
329  * @vgpu: a vGPU
332 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
334 	vfree(vgpu->mmio.vreg);
335 	vgpu->mmio.vreg = NULL;