i915/gvt/handlers.c

101 	void *p_data, unsigned int bytes)
103 	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
107 	void *p_data, unsigned int bytes)
109 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
206 		unsigned int fence_num, void *p_data, unsigned int bytes)
222 		memset(p_data, 0, bytes);
229 		unsigned int offset, void *p_data, unsigned int bytes)
231 	u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
249 	write_vreg(vgpu, offset, p_data, bytes);
254 		void *p_data, unsigned int bytes)
259 			p_data, bytes);
262 	read_vreg(vgpu, off, p_data, bytes);
267 		void *p_data, unsigned int bytes)
274 	ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
277 	write_vreg(vgpu, off, p_data, bytes);
292 		unsigned int offset, void *p_data, unsigned int bytes)
298 	new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
326 			    void *p_data, unsigned int bytes)
331 	write_vreg(vgpu, offset, p_data, bytes);
375 		void *p_data, unsigned int bytes)
377 	return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
381 		void *p_data, unsigned int bytes)
383 	return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
387 		unsigned int offset, void *p_data, unsigned int bytes)
389 	write_vreg(vgpu, offset, p_data, bytes);
405 		unsigned int offset, void *p_data, unsigned int bytes)
407 	write_vreg(vgpu, offset, p_data, bytes);
417 		void *p_data, unsigned int bytes)
419 	write_vreg(vgpu, offset, p_data, bytes);
435 		void *p_data, unsigned int bytes)
454 	read_vreg(vgpu, offset, p_data, bytes);
713 		void *p_data, unsigned int bytes)
717 	write_vreg(vgpu, offset, p_data, bytes);
786 	unsigned int offset, void *p_data, unsigned int bytes)
788 	u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
803 		intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
809 		void *p_data, unsigned int bytes)
811 	write_vreg(vgpu, offset, p_data, bytes);
825 		unsigned int offset, void *p_data, unsigned int bytes)
827 	vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
917 		unsigned int offset, void *p_data, unsigned int bytes)
934 	write_vreg(vgpu, offset, p_data, bytes);
961 		void *p_data, unsigned int bytes)
967 	write_vreg(vgpu, offset, p_data, bytes);
979 		unsigned int offset, void *p_data, unsigned int bytes)
984 	reg_val = *((u32 *)p_data);
994 		unsigned int offset, void *p_data, unsigned int bytes)
998 	write_vreg(vgpu, offset, p_data, bytes);
1007 		unsigned int offset, void *p_data, unsigned int bytes)
1011 	write_vreg(vgpu, offset, p_data, bytes);
1025 		void *p_data, unsigned int bytes)
1032 	write_vreg(vgpu, offset, p_data, bytes);
1049 		void *p_data, unsigned int bytes)
1054 	write_vreg(vgpu, offset, p_data, bytes);
1066 			       unsigned int offset, void *p_data,
1075 	write_vreg(vgpu, offset, p_data, bytes);
1182 		unsigned int offset, void *p_data, unsigned int bytes)
1196 	write_vreg(vgpu, offset, p_data, bytes);
1346 	intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1354 		void *p_data, unsigned int bytes)
1356 	*(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1357 	write_vreg(vgpu, offset, p_data, bytes);
1362 		void *p_data, unsigned int bytes)
1366 	write_vreg(vgpu, offset, p_data, bytes);
1416 		void *p_data, unsigned int bytes)
1425 	read_vreg(vgpu, offset, p_data, bytes);
1430 		void *p_data, unsigned int bytes)
1434 	write_vreg(vgpu, offset, p_data, bytes);
1459 		void *p_data, unsigned int bytes)
1463 	read_vreg(vgpu, offset, p_data, bytes);
1485 				offset, bytes, *(u32 *)p_data);
1535 		void *p_data, unsigned int bytes)
1537 	u32 data = *(u32 *)p_data;
1573 		write_vreg(vgpu, offset, p_data, bytes);
1579 		unsigned int offset, void *p_data, unsigned int bytes)
1582 	u32 val = *(u32 *)p_data;
1593 	return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1597 		unsigned int offset, void *p_data, unsigned int bytes)
1599 	write_vreg(vgpu, offset, p_data, bytes);
1612 		unsigned int offset, void *p_data, unsigned int bytes)
1614 	write_vreg(vgpu, offset, p_data, bytes);
1625 	unsigned int offset, void *p_data, unsigned int bytes)
1627 	write_vreg(vgpu, offset, p_data, bytes);
1635 		void *p_data, unsigned int bytes)
1640 	write_vreg(vgpu, offset, p_data, bytes);
1654 		void *p_data, unsigned int bytes)
1657 	u32 trtte = *(u32 *)p_data;
1665 	write_vreg(vgpu, offset, p_data, bytes);
1671 		void *p_data, unsigned int bytes)
1673 	write_vreg(vgpu, offset, p_data, bytes);
1678 		void *p_data, unsigned int bytes)
1696 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1700 		void *p_data, unsigned int bytes)
1702 	u32 value = *(u32 *)p_data;
1758 		void *p_data, unsigned int bytes)
1760 	u32 value = *(u32 *)p_data;
1789 		unsigned int offset, void *p_data, unsigned int bytes)
1791 	u32 v = *(u32 *)p_data;
1804 		void *p_data, unsigned int bytes)
1806 	u32 v = *(u32 *)p_data;
1818 		unsigned int offset, void *p_data, unsigned int bytes)
1820 	u32 v = *(u32 *)p_data;
1831 		unsigned int offset, void *p_data, unsigned int bytes)
1833 	u32 v = *(u32 *)p_data;
1844 		unsigned int offset, void *p_data, unsigned int bytes)
1846 	u32 v = *(u32 *)p_data;
1865 		unsigned int offset, void *p_data, unsigned int bytes)
1873 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1877 		unsigned int offset, void *p_data, unsigned int bytes)
1879 	u32 v = *(u32 *)p_data;
1895 		unsigned int offset, void *p_data, unsigned int bytes)
1897 	u32 v = *(u32 *)p_data;
1920 		unsigned int offset, void *p_data, unsigned int bytes)
1937 			      void *p_data, unsigned int bytes)
1955 			   unsigned int offset, void *p_data,
1959 	read_vreg(vgpu, offset, p_data, bytes);
1965 		unsigned int offset, void *p_data, unsigned int bytes)
1990 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1994 		void *p_data, unsigned int bytes)
1999 	u32 data = *(u32 *)p_data;
2036 		void *p_data, unsigned int bytes)
2038 	u32 data = *(u32 *)p_data;
2044 	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
2047 		(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
2048 	write_vreg(vgpu, offset, p_data, bytes);
2095 		unsigned int offset, void *p_data, unsigned int bytes)
2099 	write_vreg(vgpu, offset, p_data, bytes);
2127 	unsigned int offset, void *p_data, unsigned int bytes)
2131 	write_vreg(vgpu, offset, p_data, bytes);
2144 				    unsigned int offset, void *p_data,
2147 	u32 data = *(u32 *)p_data;
2149 	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
2150 	write_vreg(vgpu, offset, p_data, bytes);
3073  * @p_data: data return buffer
3080 		void *p_data, unsigned int bytes)
3082 	read_vreg(vgpu, offset, p_data, bytes);
3090  * @p_data: write data buffer
3097 		void *p_data, unsigned int bytes)
3099 	write_vreg(vgpu, offset, p_data, bytes);
3107  * @p_data: write data buffer
3114 		void *p_data, unsigned int bytes)
3119 	write_vreg(vgpu, offset, p_data, bytes);