i915/gvt/edid.c

55 static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
57 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
74 	if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
76 			intel_vgpu_port(vgpu, edid->port)->edid;
132 static void reset_gmbus_controller(struct intel_vgpu *vgpu)
134 	vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
135 	if (!vgpu->display.i2c_edid.edid_available)
136 		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
137 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
141 static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
144 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
147 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
149 	pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
151 	intel_vgpu_init_i2c_edid(vgpu);
165 	vgpu->display.i2c_edid.state = I2C_GMBUS;
166 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
168 	vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
169 	vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
171 	if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
172 			!intel_vgpu_port_is_dp(vgpu, port)) {
173 		vgpu->display.i2c_edid.port = port;
174 		vgpu->display.i2c_edid.edid_available = true;
175 		vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
177 		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
181 static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
184 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
188 	if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
190 			vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
191 			reset_gmbus_controller(vgpu);
204 			vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
205 			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
218 		/* vgpu gmbus only support EDID */
223 				"vgpu%d: unsupported gmbus target addr(0x%x)\n"
225 					vgpu->id, target_addr);
243 			if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
245 				intel_vgpu_init_i2c_edid(vgpu);
253 				vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
265 			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
277 		vgpu_vreg(vgpu, offset) = wvalue;
282 static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
285 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
291 static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
296 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
303 	if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
305 			memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
312 			byte_data = edid_get_byte(vgpu);
316 		memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
317 		memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
331 			intel_vgpu_init_i2c_edid(vgpu);
338 		memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
344 static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
347 	u32 value = vgpu_vreg(vgpu, offset);
349 	if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
350 		vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
355 static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
361 		vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
368  * @vgpu: a vGPU
379 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
382 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
388 		return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
390 		return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
392 	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
398  * @vgpu: a vGPU
409 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
412 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
418 		return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
420 		return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
422 		return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
424 		return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
426 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
471  * @vgpu: a vGPU
479 void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
484 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
485 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
493 		vgpu_vreg(vgpu, offset) = value;
500 	msg = vgpu_vreg(vgpu, offset + 4);
511 	vgpu_vreg(vgpu, offset) =
518 			intel_vgpu_init_i2c_edid(vgpu);
525 				intel_vgpu_init_i2c_edid(vgpu);
530 				if (intel_vgpu_has_monitor_on_port(vgpu,
532 					intel_vgpu_port_is_dp(vgpu, port_idx))
549 			unsigned char val = edid_get_byte(vgpu);
560 	vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
565  * @vgpu: a vGPU
570 void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
572 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;