i915/gvt/cmd_parser.c

481 	struct intel_vgpu *vgpu;
522 	(s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
738 	gvt_dbg_cmd("  vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
740 		    s->vgpu->id, s->engine->name,
863 	struct intel_vgpu *vgpu = s->vgpu;
873 		mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
897 	struct intel_vgpu *vgpu = s->vgpu;
898 	struct intel_gvt *gvt = vgpu->gvt;
957 	vreg = &vgpu_vreg(s->vgpu, offset);
988 				ret = mmio_info->write(s->vgpu, offset,
1019 		intel_gvt_read_gpa(s->vgpu,
1025 			if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
1026 				intel_vgpu_mask_mmio_write(vgpu,
1029 				vgpu_vreg(vgpu, offset) = data;
1097 	struct intel_gvt *gvt = s->vgpu->gvt;
1126 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1184 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1216 					hws_pga = s->vgpu->hws_pga[s->engine->id];
1339 	struct intel_vgpu *vgpu = s->vgpu;
1403 		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1404 		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1407 		stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1409 		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1427 	struct intel_vgpu *vgpu = s->vgpu;
1429 	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1432 		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1434 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1437 		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1439 		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1444 		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;
1447 		intel_vgpu_trigger_virtual_event(vgpu, info->event);
1449 		set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1481 	struct intel_vgpu *vgpu = s->vgpu;
1543 	struct intel_vgpu *vgpu = s->vgpu;
1544 	int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1564 	struct intel_vgpu *vgpu = s->vgpu;
1565 	u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1580 	} else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1599 			vgpu->id,
1600 			vgpu_aperture_gmadr_base(vgpu),
1601 			vgpu_aperture_gmadr_end(vgpu),
1602 			vgpu_hidden_gmadr_base(vgpu),
1603 			vgpu_hidden_gmadr_end(vgpu));
1609 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1642 	struct intel_vgpu *vgpu = s->vgpu;
1666 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1716 	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1744 			hws_pga = s->vgpu->hws_pga[s->engine->id];
1767 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1786 		intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len);
1803 	    !(s->vgpu->scan_nonprivbb & s->engine->mask))
1822 	struct intel_vgpu *vgpu = s->vgpu;
1825 		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1836 	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1845 		if (copy_gma_to_hva(s->vgpu, mm,
1848 		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1878 	struct intel_vgpu *vgpu = s->vgpu;
1882 	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1901 	struct intel_vgpu *vgpu = s->vgpu;
1908 		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1955 	ret = copy_gma_to_hva(s->vgpu, mm,
2003 	struct intel_vgpu *vgpu = s->vgpu;
2731 	struct intel_vgpu *vgpu = s->vgpu;
2742 		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2754 	trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2803 	struct intel_vgpu *vgpu = s->vgpu;
2856 	s.vgpu = workload->vgpu;
2903 	s.vgpu = workload->vgpu;
2925 	struct intel_vgpu *vgpu = workload->vgpu;
2926 	struct intel_vgpu_submission *s = &vgpu->submission;
2962 		ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2973 	ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2985 	struct intel_vgpu *vgpu = workload->vgpu;
3008 	struct intel_vgpu *vgpu = workload->vgpu;
3035 	ret = copy_gma_to_hva(workload->vgpu,
3036 				workload->vgpu->gtt.ggtt_mm,
3080 	struct intel_vgpu *vgpu = workload->vgpu;
3107 void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
3110 	struct intel_gvt *gvt = vgpu->gvt;
3135 		s.vgpu = vgpu;
3164 	struct intel_vgpu *vgpu = workload->vgpu;
3168 	struct intel_context *ce = vgpu->submission.shadow[ring_id];
3187 	s.vgpu = workload->vgpu;