i915/gvt/cfg_space.c

60  * @vgpu: target vgpu
69 static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,
72 	u8 *cfg_base = vgpu_cfg_space(vgpu);
97 	if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) {
98 		pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off])
101 			vgpu->d3_entered = true;
102 		gvt_dbg_core("vgpu-%d power status changed to %d\n",
103 			     vgpu->id, pwr);
109  * @vgpu: target vgpu
117 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
120 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
126 			offset + bytes > vgpu->gvt->device_info.cfg_space_size))
129 	memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
133 static void map_aperture(struct intel_vgpu *vgpu, bool map)
135 	if (map != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
136 		vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
139 static void trap_gttmmio(struct intel_vgpu *vgpu, bool trap)
141 	if (trap != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)
142 		vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;
145 static int emulate_pci_command_write(struct intel_vgpu *vgpu,
148 	u8 old = vgpu_cfg_space(vgpu)[offset];
152 	vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
157 		trap_gttmmio(vgpu, false);
158 		map_aperture(vgpu, false);
160 		trap_gttmmio(vgpu, true);
161 		map_aperture(vgpu, true);
167 static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu,
170 	u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
177 		vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
181 static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
188 		vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
189 	struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;
203 			intel_vgpu_write_pci_bar(vgpu, offset,
209 			trap_gttmmio(vgpu, false);
214 			intel_vgpu_write_pci_bar(vgpu, offset,
216 			map_aperture(vgpu, false);
220 			intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false);
230 			trap_gttmmio(vgpu, false);
231 			intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
232 			trap_gttmmio(vgpu, mmio_enabled);
236 			map_aperture(vgpu, false);
237 			intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
238 			map_aperture(vgpu, mmio_enabled);
241 			intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
248  * @vgpu: target vgpu
256 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
259 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
266 			offset + bytes > vgpu->gvt->device_info.cfg_space_size))
273 		return emulate_pci_command_write(vgpu, offset, p_data, bytes);
280 		return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);
285 		emulate_pci_bar_write(vgpu, offset, p_data, bytes);
290 		ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);
298 		ret = intel_vgpu_opregion_base_write_handler(vgpu,
303 		vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
306 		vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
315  * @vgpu: a vGPU
319 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
322 	struct intel_gvt *gvt = vgpu->gvt;
328 	memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
332 		vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =
334 		vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =
339 	gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);
342 	intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2,
345 	vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO
351 	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
352 	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
353 	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
354 	memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
356 	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
358 	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
361 	memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
364 	vgpu->cfg_space.pmcsr_off = 0;
365 	if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) {
366 		next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST];
368 			if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) {
369 				vgpu->cfg_space.pmcsr_off = next + PCI_PM_CTRL;
372 			next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT];
380  * @vgpu: a vGPU
383 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu)
385 	u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND];
386 	bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] !=
390 		trap_gttmmio(vgpu, false);
391 		map_aperture(vgpu, false);
399 	intel_vgpu_init_cfg_space(vgpu, primary);