i915/gt/selftest_workarounds.c

34 	} engine[I915_NUM_ENGINES];
64 	struct intel_engine_cs *engine;
73 	for_each_engine(engine, gt, id) {
74 		struct i915_wa_list *wal = &lists->engine[id].wa_list;
76 		wa_init_start(wal, gt, "REF", engine->name);
77 		engine_init_workarounds(engine, wal);
80 		__intel_engine_init_ctx_wa(engine,
81 					   &lists->engine[id].ctx_wa_list,
89 	struct intel_engine_cs *engine;
92 	for_each_engine(engine, gt, id)
93 		intel_wa_list_free(&lists->engine[id].wa_list);
101 	struct intel_engine_cs *engine = ce->engine;
102 	const u32 base = engine->mmio_base;
110 	result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
125 	vma = i915_vma_instance(result, &engine->gt->ggtt->vm, NULL);
146 	if (GRAPHICS_VER(engine->i915) >= 8)
178 get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)
180 	i915_reg_t reg = i < engine->whitelist.count ?
181 			 engine->whitelist.list[i].reg :
182 			 RING_NOPID(engine->mmio_base);
188 print_results(const struct intel_engine_cs *engine, const u32 *results)
193 		u32 expected = get_whitelist_reg(engine, i);
203 	struct intel_engine_cs *engine = ce->engine;
216 	intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */
219 	if (intel_gt_is_wedged(engine->gt))
231 		u32 expected = get_whitelist_reg(engine, i);
235 			print_results(engine, vaddr);
251 static int do_device_reset(struct intel_engine_cs *engine)
253 	intel_gt_reset(engine->gt, engine->mask, "live_workarounds");
257 static int do_engine_reset(struct intel_engine_cs *engine)
259 	return intel_engine_reset(engine, "live_workarounds");
262 static int do_guc_reset(struct intel_engine_cs *engine)
269 switch_to_scratch_context(struct intel_engine_cs *engine,
276 	ce = intel_context_create(engine);
297 static int check_whitelist_across_reset(struct intel_engine_cs *engine,
308 		engine->whitelist.count, engine->name, name);
310 	ce = intel_context_create(engine);
314 	err = igt_spinner_init(&spin, engine->gt);
324 	err = switch_to_scratch_context(engine, &spin, &rq);
335 	with_intel_runtime_pm(engine->uncore->rpm, wakeref)
336 		err = reset(engine);
338 	/* Ensure the reset happens and kills the engine */
356 	tmp = intel_context_create(engine);
418 static bool wo_register(struct intel_engine_cs *engine, u32 reg)
420 	enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
436 static bool timestamp(const struct intel_engine_cs *engine, u32 reg)
438 	reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
459 static int whitelist_writable_count(struct intel_engine_cs *engine)
461 	int count = engine->whitelist.count;
464 	for (i = 0; i < engine->whitelist.count; i++) {
465 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
502 	struct intel_engine_cs *engine = ce->engine;
519 	for (i = 0; i < engine->whitelist.count; i++) {
520 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
529 		if (wo_register(engine, reg))
532 		if (timestamp(engine, reg))
565 		if (GRAPHICS_VER(engine->i915) >= 8)
569 			 engine->name, reg);
616 		intel_gt_chipset_flush(engine->gt);
625 		if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
626 			err = engine->emit_init_breadcrumb(rq);
640 		err = engine->emit_bb_start(rq,
650 			       engine->name, reg);
651 			intel_gt_set_wedged(engine->gt);
661 				       engine->name, reg);
693 			       engine->name, err, reg);
697 					engine->name, reg, results[0]);
700 					engine->name, reg, results[0], rsvd);
747 	if (igt_flush_test(engine->i915))
759 	struct intel_engine_cs *engine;
767 	for_each_engine(engine, gt, id) {
771 		if (engine->whitelist.count == 0)
774 		ce = intel_context_create(engine);
790 	struct intel_engine_cs *engine;
797 	for_each_engine(engine, gt, id) {
798 		if (engine->whitelist.count == 0)
802 			if (intel_engine_uses_guc(engine)) {
806 				err = intel_selftest_modify_policy(engine, &saved,
811 				err = check_whitelist_across_reset(engine,
815 				err2 = intel_selftest_restore_policy(engine, &saved);
819 				err = check_whitelist_across_reset(engine,
821 								   "engine");
829 			err = check_whitelist_across_reset(engine,
845 	struct intel_engine_cs *engine = ce->engine;
859 	if (GRAPHICS_VER(engine->i915) >= 8)
862 	cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
868 	for (i = 0; i < engine->whitelist.count; i++) {
870 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
888 	struct intel_engine_cs *engine = ce->engine;
904 	*cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine));
905 	for (i = 0; i < engine->whitelist.count; i++) {
906 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
920 	intel_gt_chipset_flush(engine->gt);
928 	if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
929 		err = engine->emit_init_breadcrumb(rq);
939 	err = engine->emit_bb_start(rq, i915_vma_offset(batch), 0, 0);
984 static bool result_eq(struct intel_engine_cs *engine,
987 	if (a != b && !pardon_reg(engine->i915, reg)) {
1006 static bool result_neq(struct intel_engine_cs *engine,
1009 	if (a == b && !writeonly_reg(engine->i915, reg)) {
1019 check_whitelisted_registers(struct intel_engine_cs *engine,
1022 			    bool (*fn)(struct intel_engine_cs *engine,
1040 	for (i = 0; i < engine->whitelist.count; i++) {
1041 		const struct i915_wa *wa = &engine->whitelist.list[i];
1047 		if (!fn(engine, a[i], b[i], wa->reg))
1063 	struct intel_engine_cs *engine;
1092 	for_each_engine(engine, gt, id) {
1095 		if (!engine->kernel_context->vm)
1098 		if (!whitelist_writable_count(engine))
1101 		ce[0] = intel_context_create(engine);
1106 		ce[1] = intel_context_create(engine);
1129 		err = check_whitelisted_registers(engine,
1142 		err = check_whitelisted_registers(engine,
1169 	struct intel_engine_cs *engine;
1175 	for_each_engine(engine, gt, id) {
1178 		ce = intel_context_create(engine);
1183 					    &lists->engine[id].wa_list,
1187 					    &lists->engine[id].ctx_wa_list,
1239 	struct intel_engine_cs *engine;
1260 	for_each_engine(engine, gt, id) {
1262 		bool using_guc = intel_engine_uses_guc(engine);
1266 		pr_info("Verifying after %s reset...\n", engine->name);
1267 		ret = intel_selftest_modify_policy(engine, &saved,
1272 		ce = intel_context_create(engine);
1285 			ret = intel_engine_reset(engine, "live_workarounds:idle");
1287 				pr_err("%s: Reset failed while idle\n", engine->name);
1298 		ret = igt_spinner_init(&spin, engine->gt);
1311 			pr_err("%s: Spinner failed to start\n", engine->name);
1323 			ret = intel_engine_reset(engine, "live_workarounds:active");
1326 				       engine->name);
1332 		/* Ensure the reset happens and kills the engine */
1348 		ret2 = intel_selftest_restore_policy(engine, &saved);