i915/gt/intel_sseu.c

48 			int subslice)
52 		return sseu->eu_mask.xehp[subslice];
54 		return sseu->eu_mask.hsw[slice][subslice];
58 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
64 		sseu->eu_mask.xehp[subslice] = eu_mask;
66 		sseu->eu_mask.hsw[slice][subslice] = eu_mask;
119  * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
121  * @sseu: SSEU structure containing subslice mask to copy
123  * Copies the subslice mask to a userspace buffer in the format expected by
366 	 * CHV supports subslice power gating on devices with more than
367 	 * one subslice, and supports EU power gating on devices with
368 	 * more than one EU pair per subslice.
392 	 * The subslice disable field is global, i.e. it applies
415 				/* skip disabled subslice */
426 			 * Record which subslice(s) has(have) 7 EUs. we
440 	 * EU in any one subslice may be fused off for die
452 	 * more than one EU pair per subslice. BXT+ supports subslice
453 	 * power gating on devices with more than one subslice, and
455 	 * pair per subslice.
493 	 * The subslice disable field is global, i.e. it applies
526 				/* skip disabled subslice */
548 	 * subslices with the exception that any one EU in any one subslice may
663 	 * slice/subslice/EU enablement prior to Gen9.
690 	 * If enabled subslice count is greater than four, two whole slices must
694 	 * When more than one slice is enabled, hardware ignores the subslice
714 	 * slice/subslice/EU in a partially enabled state. We
772 		drm_printf(p, "subslice total: %u\n",
783 		drm_printf(p, "subslice total: %u\n",
795 	drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
798 	drm_printf(p, "has subslice power gating: %s\n",
812 		drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",