i915/display/intel_dpll_mgr.c

3551 	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
3558 	val = intel_de_read(display, enable_reg);
3682 				 i915_reg_t enable_reg)
3695 	val = intel_de_read(display, enable_reg);
3744 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
3746 	return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
3908 				 i915_reg_t enable_reg)
3910 	intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
3916 	if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1))
3923 			   i915_reg_t enable_reg)
3925 	intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
3928 	if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1))
3961 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
3963 	icl_pll_power_enable(display, pll, enable_reg);
3973 	icl_pll_enable(display, pll, enable_reg);
4006 	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
4008 	icl_pll_power_enable(display, pll, enable_reg);
4021 	icl_pll_enable(display, pll, enable_reg);
4028 			    i915_reg_t enable_reg)
4038 	intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
4041 	if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1))
4046 	intel_de_rmw(display, enable_reg, PLL_POWER_ENABLE, 0);
4052 	if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1))
4060 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
4062 	icl_pll_disable(display, pll, enable_reg);
4074 	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
4076 	icl_pll_disable(display, pll, enable_reg);