i915/display/intel_display_device.c

79 #define PIPE_A_OFFSET		0x70000
80 #define PIPE_B_OFFSET		0x71000
81 #define PIPE_C_OFFSET		0x72000
82 #define PIPE_D_OFFSET		0x73000
83 #define CHV_PIPE_C_OFFSET	0x74000
90 #define PIPE_EDP_OFFSET	0x7f000
92 /* ICL DSI 0 and 1 */
93 #define PIPE_DSI0_OFFSET	0x7b000
94 #define PIPE_DSI1_OFFSET	0x7b800
96 #define TRANSCODER_A_OFFSET 0x60000
97 #define TRANSCODER_B_OFFSET 0x61000
98 #define TRANSCODER_C_OFFSET 0x62000
99 #define CHV_TRANSCODER_C_OFFSET 0x63000
100 #define TRANSCODER_D_OFFSET 0x63000
101 #define TRANSCODER_EDP_OFFSET 0x6f000
102 #define TRANSCODER_DSI0_OFFSET	0x6b000
103 #define TRANSCODER_DSI1_OFFSET	0x6b800
105 #define CURSOR_A_OFFSET 0x70080
106 #define CURSOR_B_OFFSET 0x700c0
107 #define CHV_CURSOR_C_OFFSET 0x700e0
108 #define IVB_CURSOR_B_OFFSET 0x71080
109 #define IVB_CURSOR_C_OFFSET 0x72080
110 #define TGL_CURSOR_D_OFFSET 0x73080
544 	0
550 	0
595 	0
603 	0
690 	0
696 	0
700 	[0x6] = STEP_G0,
701 	[0x7] = STEP_H0,
702 	[0x9] = STEP_J0,
703 	[0xA] = STEP_I1,
727 	0
734 	0
770 	0
775 	0
797 	0
836 	[0xA] = STEP_C0,
837 	[0xB] = STEP_C0,
838 	[0xC] = STEP_D0,
839 	[0xD] = STEP_E0,
870 	.abox_mask = BIT(0), \
912 	0
943 	[0] = STEP_A0,
1004 	0
1008 	[0] = STEP_B0,
1013 	[0] = STEP_A0,
1043 	[0] = STEP_A0,
1060 	[0] = STEP_A0,
1069 		.abox_mask = BIT(0),
1071 		.has_psr_hw_tracking = 0,
1084 	0
1088 	[0x0] = STEP_A0,
1089 	[0x1] = STEP_A2,
1090 	[0x4] = STEP_B0,
1091 	[0x8] = STEP_B0,
1092 	[0xC] = STEP_C0,
1096 	[0x4] = STEP_D0,
1097 	[0xC] = STEP_C0,
1113 		.has_psr_hw_tracking = 0,
1122 	.abox_mask = GENMASK(1, 0),						\
1167 	.has_psr_hw_tracking = 0,
1179 	0
1184 	0
1189 	0
1193 	[0x0] = STEP_A0,
1194 	[0x4] = STEP_B0,
1195 	[0x8] = STEP_C0,
1196 	[0xC] = STEP_D0,
1200 	[0x0] = STEP_D0,
1204 	[0x4] = STEP_E0,
1244 	0
1249 	0
1254 	0
1258 	[0x0] = STEP_A0,
1259 	[0x1] = STEP_A0,
1260 	[0x4] = STEP_B0,
1261 	[0x8] = STEP_C0,
1265 	[0x0] = STEP_B0,
1266 	[0x4] = STEP_C0,
1267 	[0x5] = STEP_C0,
1271 	[0x0] = STEP_C0,
1272 	[0x1] = STEP_C0,
1300 	.abox_mask = GENMASK(1, 0),						\
1366 	0
1409 		INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, 0),
1479 	{ 14,  0, &xe_lpdp_display },
1481 	{ 20,  0, &xe2_lpd_display },
1482 	{ 30,  0, &xe2_lpd_display },
1495 	addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
1505 	if (val == 0) {
1514 	for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) {
1532 	for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
1577 		drm_warn(display->drm, "Unknown revision 0x%02x\n", revision);
1585 		 * it's better than defaulting to 0.
1591 			drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n",
1608 	return sizeof(((struct intel_display_platforms *)0)->bitmap) * BITS_PER_BYTE;
1743 			display_runtime->num_scalers[pipe] = 0;
1797 		 * reads don't land anywhere. In that case, we read 0s.
1844 			display_runtime->has_hdcp = 0;
1848 				display_runtime->fbc_mask = 0;
1852 			display_runtime->has_dmc = 0;
1856 			display_runtime->has_dsc = 0;
1868 			display_runtime->has_dsc = 0;
1889 	memset(display_runtime, 0, sizeof(*display_runtime));