i915/display/intel_combo_phy.c

58 icl_get_procmon_ref_values(struct intel_display *display, enum phy phy)
62 	val = intel_de_read(display, ICL_PORT_COMP_DW3(phy));
81 				       enum phy phy)
85 	procmon = icl_get_procmon_ref_values(display, phy);
87 	intel_de_rmw(display, ICL_PORT_COMP_DW1(phy),
90 	intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9);
91 	intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10);
95 			  enum phy phy, i915_reg_t reg, u32 mask,
102 			    "Combo PHY %c reg %08x state mismatch: "
104 			    phy_name(phy),
113 					  enum phy phy)
118 	procmon = icl_get_procmon_ref_values(display, phy);
120 	ret = check_phy_reg(display, phy, ICL_PORT_COMP_DW1(phy),
122 	ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW9(phy),
124 	ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW10(phy),
130 static bool has_phy_misc(struct intel_display *display, enum phy phy)
133 	 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
134 	 * PHY-B and may not even have instances of the register for the
135 	 * other combo PHY's.
138 	 * that we program it for PHY A.
142 		return phy == PHY_A;
146 		return phy < PHY_C;
152 				  enum phy phy)
154 	/* The PHY C added by EHL has no PHY_MISC register */
155 	if (!has_phy_misc(display, phy))
156 		return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
158 		return !(intel_de_read(display, ICL_PHY_MISC(phy)) &
160 			(intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
171 	 * the PHY.  So if combo PHY A is wired up to drive an external
185 			"VBT claims to have both internal and external displays on PHY A.  Configuring for internal.\n");
190 static bool phy_is_master(struct intel_display *display, enum phy phy)
205 	 * We must set the IREFGEN bit for any PHY acting as a master
206 	 * to another PHY.
208 	if (phy == PHY_A)
211 		return phy == PHY_D;
213 		return phy == PHY_C;
219 				       enum phy phy)
224 	if (!icl_combo_phy_enabled(display, phy))
228 		ret &= check_phy_reg(display, phy, ICL_PORT_TX_DW8_LN(0, phy),
234 		ret &= check_phy_reg(display, phy, ICL_PORT_PCS_DW1_LN(0, phy),
238 	ret &= icl_verify_procmon_ref_values(display, phy);
240 	if (phy_is_master(display, phy)) {
241 		ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW8(phy),
248 			ret &= check_phy_reg(display, phy, ICL_PHY_MISC(phy),
254 	ret &= check_phy_reg(display, phy, ICL_PORT_CL_DW5(phy),
261 				    enum phy phy, bool is_dsi,
305 	intel_de_rmw(display, ICL_PORT_CL_DW10(phy),
311 	enum phy phy;
313 	for_each_combo_phy(display, phy) {
317 		if (icl_combo_phy_verify_state(display, phy))
320 		procmon = icl_get_procmon_ref_values(display, phy);
323 			    "Initializing combo PHY %c (Voltage/Process Info : %s)\n",
324 			    phy_name(phy), procmon->name);
326 		if (!has_phy_misc(display, phy))
330 		 * EHL's combo PHY A can be hooked up to either an external
333 		 * can't be changed on the fly, so initialize the PHY's mux
337 		val = intel_de_read(display, ICL_PHY_MISC(phy));
339 		    phy == PHY_A) {
347 		intel_de_write(display, ICL_PHY_MISC(phy), val);
351 			val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy));
355 			intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val);
357 			val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
360 			intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
363 		icl_set_procmon_ref_values(display, phy);
365 		if (phy_is_master(display, phy))
366 			intel_de_rmw(display, ICL_PORT_COMP_DW8(phy),
369 		intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);
370 		intel_de_rmw(display, ICL_PORT_CL_DW5(phy),
377 	enum phy phy;
379 	for_each_combo_phy_reverse(display, phy) {
380 		if (phy == PHY_A &&
381 		    !icl_combo_phy_verify_state(display, phy)) {
389 					    "Combo PHY %c HW state changed unexpectedly\n",
390 					    phy_name(phy));
393 					 "Combo PHY %c HW state changed unexpectedly\n",
394 					 phy_name(phy));
398 		if (!has_phy_misc(display, phy))
401 		intel_de_rmw(display, ICL_PHY_MISC(phy), 0,
405 		intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);