i915/display/intel_bw.c

257 			      const struct dram_info *dram_info,
263 	qi->num_points = dram_info->num_qgv_points;
264 	qi->num_psf_points = dram_info->num_psf_gv_points;
267 		switch (dram_info->type) {
292 			MISSING_CASE(dram_info->type);
296 		switch (dram_info->type) {
330 		qi->t_bl = dram_info->type == INTEL_DRAM_DDR4 ? 4 : 8;
464 			   const struct dram_info *dram_info,
469 	int num_channels = max_t(u8, 1, dram_info->num_channels);
476 	ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile);
535 			   const struct dram_info *dram_info,
540 	int num_channels = max_t(u8, 1, dram_info->num_channels);
548 	ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile);
556 	    (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5))
678 			       const struct dram_info *dram_info,
682 	int num_channels = dram_info->num_channels;
686 	ret = icl_get_qgv_points(display, dram_info, &qi, true);
809 	const struct dram_info *dram_info = intel_dram_info(display->drm);
815 		tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
817 		tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
819 		 dram_info->type == INTEL_DRAM_GDDR_ECC)
820 		xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
822 		xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
824 		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
828 		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
830 		tgl_get_bw_info(display, dram_info, &adls_sa_info);
832 		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
834 		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
836 		icl_get_bw_info(display, dram_info, &icl_sa_info);