drm/etnaviv/etnaviv_iommu_v2.c

165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu,
172 	if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE)
175 	if (gpu->mmu_context)
176 		etnaviv_iommu_context_put(gpu->mmu_context);
177 	gpu->mmu_context = etnaviv_iommu_context_get(context);
179 	prefetch = etnaviv_buffer_config_mmuv2(gpu,
182 	etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer),
184 	etnaviv_gpu_wait_idle(gpu, 100);
186 	gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE);
189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu,
196 	if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE)
199 	if (gpu->mmu_context)
200 		etnaviv_iommu_context_put(gpu->mmu_context);
201 	gpu->mmu_context = etnaviv_iommu_context_get(context);
203 	gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW,
205 	gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH,
207 	gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE);
209 	gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW,
211 	gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW,
213 	gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG,
223 	prefetch = etnaviv_buffer_config_pta(gpu, v2_context->id);
224 	etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer),
226 	etnaviv_gpu_wait_idle(gpu, 100);
228 	gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE);
244 static void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu,
247 	switch (gpu->sec_mode) {
249 		etnaviv_iommuv2_restore_nonsec(gpu, context);
252 		etnaviv_iommuv2_restore_sec(gpu, context);